Lines Matching +full:sram +full:- +full:others
44 (((vpi) << card->vcibits) | ((vci) & card->vcimask))
107 #define SAR_FB_SIZE_0 (2048 - 256)
108 #define SAR_FB_SIZE_1 (4096 - 256)
109 #define SAR_FB_SIZE_2 (8192 - 256)
110 #define SAR_FB_SIZE_3 (16384 - 256)
158 #define SCQ_MASK (SCQ_SIZE - 1)
228 /* RCTE - Receive Connection Table Entry */
242 /* RSQ - Receive Status Queue */
280 /* TSQ - Transmit Status Queue */
335 #define FBQ_MASK (FBQ_SIZE - 1)
344 #define POOL_QUEUE(handle) (((handle) >> 16) - 1)
356 unsigned long srambase; /* SAR's sram base address */
360 spinlock_t cmd_lock; /* for r/w utility/sram */
367 unsigned long tct_base; /* TCT base address in SRAM */
368 unsigned long rct_base; /* RCT base address in SRAM */
369 unsigned long rt_base; /* Rate Table base in SRAM */
370 unsigned long scd_base; /* SCD base address in SRAM */
371 unsigned long tst[2]; /* TST base address in SRAM */
372 unsigned long abrst_base; /* ABRST base address in SRAM */
373 unsigned long fifo_base; /* RX FIFO base in SRAM */
377 unsigned int sramsize; /* SAR's sram size */
432 ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))
441 #define SAR_REG_DR0 (card->membase + 0x00)
442 #define SAR_REG_DR1 (card->membase + 0x04)
443 #define SAR_REG_DR2 (card->membase + 0x08)
444 #define SAR_REG_DR3 (card->membase + 0x0C)
445 #define SAR_REG_CMD (card->membase + 0x10)
446 #define SAR_REG_CFG (card->membase + 0x14)
447 #define SAR_REG_STAT (card->membase + 0x18)
448 #define SAR_REG_RSQB (card->membase + 0x1C)
449 #define SAR_REG_RSQT (card->membase + 0x20)
450 #define SAR_REG_RSQH (card->membase + 0x24)
451 #define SAR_REG_CDC (card->membase + 0x28)
452 #define SAR_REG_VPEC (card->membase + 0x2C)
453 #define SAR_REG_ICC (card->membase + 0x30)
454 #define SAR_REG_RAWCT (card->membase + 0x34)
455 #define SAR_REG_TMR (card->membase + 0x38)
456 #define SAR_REG_TSTB (card->membase + 0x3C)
457 #define SAR_REG_TSQB (card->membase + 0x40)
458 #define SAR_REG_TSQT (card->membase + 0x44)
459 #define SAR_REG_TSQH (card->membase + 0x48)
460 #define SAR_REG_GP (card->membase + 0x4C)
461 #define SAR_REG_VPM (card->membase + 0x50)
462 #define SAR_REG_RXFD (card->membase + 0x54)
463 #define SAR_REG_RXFT (card->membase + 0x58)
464 #define SAR_REG_RXFH (card->membase + 0x5C)
465 #define SAR_REG_RAWHND (card->membase + 0x60)
466 #define SAR_REG_RXSTAT (card->membase + 0x64)
467 #define SAR_REG_ABRSTD (card->membase + 0x68)
468 #define SAR_REG_ABRRQ (card->membase + 0x6C)
469 #define SAR_REG_VBRRQ (card->membase + 0x70)
470 #define SAR_REG_RTBL (card->membase + 0x74)
471 #define SAR_REG_MDFCT (card->membase + 0x78)
472 #define SAR_REG_TXSTAT (card->membase + 0x7C)
473 #define SAR_REG_TCMDQ (card->membase + 0x80)
474 #define SAR_REG_IRCP (card->membase + 0x84)
475 #define SAR_REG_FBQP0 (card->membase + 0x88)
476 #define SAR_REG_FBQP1 (card->membase + 0x8C)
477 #define SAR_REG_FBQP2 (card->membase + 0x90)
478 #define SAR_REG_FBQP3 (card->membase + 0x94)
479 #define SAR_REG_FBQS0 (card->membase + 0x98)
480 #define SAR_REG_FBQS1 (card->membase + 0x9C)
481 #define SAR_REG_FBQS2 (card->membase + 0xA0)
482 #define SAR_REG_FBQS3 (card->membase + 0xA4)
483 #define SAR_REG_FBQWP0 (card->membase + 0xA8)
484 #define SAR_REG_FBQWP1 (card->membase + 0xAC)
485 #define SAR_REG_FBQWP2 (card->membase + 0xB0)
486 #define SAR_REG_FBQWP3 (card->membase + 0xB4)
487 #define SAR_REG_NOW (card->membase + 0xB8)
611 /* SAR local SRAM layout for 128k work SRAM */
648 /* SAR local SRAM layout for 32k work SRAM */
680 /* TSR - Transmit Status Request */
692 /* TBD - Transmit Buffer Descriptor */
715 /* RXFD - Receive FIFO Descriptor */
735 /* ABRSTD - ABR + VBR Schedule Tables */
751 /* RCTE - Receive Connection Table Entry */
760 #define SAR_RCTE_FBP_01 0x00000000 /* 1. cell->FBQ0, others->FBQ1 */
795 (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
797 (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)
799 (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)