Lines Matching +full:0 +full:xffffe0ff
50 group 0 is used for all traffic
51 interrupt queue 0 is used for all interrupts
93 #define HPRINTK(fmt,args...) do { } while (0)
126 CLK_HIGH, /* 0 */
128 CLK_HIGH, /* 0 */
130 CLK_HIGH, /* 0 */
132 CLK_HIGH, /* 0 */
134 CLK_HIGH, /* 0 */
136 CLK_HIGH, /* 0 */
176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
220 #define he_mkcid(dev, vpi, vci) (((vpi << (dev)->vcibits) | vci) & 0x1fff)
225 he_writel_tcm(dev, val, CONFIG_TSRA | (cid << 3) | 0)
227 he_readl_tcm(dev, CONFIG_TSRA | (cid << 3) | 0)
243 * NOTE While the transmit connection is active, bits 23 through 0
270 he_writel_tcm(dev, val, CONFIG_TSRB | (cid << 2) | 0)
283 he_writel_tcm(dev, val, CONFIG_TSRC | (cid << 1) | 0)
302 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 0)
304 he_readl_rcm(dev, 0x00000 | (cid << 3) | 0)
307 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 1)
310 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 2)
313 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 3)
316 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 4)
319 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 5)
322 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 6)
325 he_writel_rcm(dev, val, 0x00000 | (cid << 3) | 7)
356 int err = 0; in he_init_one()
362 if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(32)) != 0) { in he_init_one()
398 return 0; in he_init_one()
431 unsigned exp = 0; in rate_to_atmf()
433 if (rate == 0) in rate_to_atmf()
434 return 0; in rate_to_atmf()
437 while (rate > 0x3ff) { in rate_to_atmf()
442 return (NONZERO | (exp << 9) | (rate & 0x1ff)); in rate_to_atmf()
452 lbufd_index = 0; in he_init_rx_lbfp0()
457 for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) { in he_init_rx_lbfp0()
465 lbuf_count = 0; in he_init_rx_lbfp0()
487 for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) { in he_init_rx_lbfp1()
495 lbuf_count = 0; in he_init_rx_lbfp1()
517 for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) { in he_init_tx_lbfp()
525 lbuf_count = 0; in he_init_tx_lbfp()
549 he_writel(he_dev, 0, TPDRQ_T); in he_init_tpdrq()
552 return 0; in he_init_tpdrq()
562 for (reg = 0; reg < 0x20; ++reg) in he_init_cs_block()
563 he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg); in he_init_cs_block()
571 for (reg = 0; reg < 0x10; ++reg) { in he_init_cs_block()
585 he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0); in he_init_cs_block()
586 he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1); in he_init_cs_block()
587 he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2); in he_init_cs_block()
588 he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3); in he_init_cs_block()
589 he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4); in he_init_cs_block()
592 he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0); in he_init_cs_block()
593 he_writel_mbox(he_dev, 0x1801, CS_ERCTL1); in he_init_cs_block()
594 he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2); in he_init_cs_block()
595 he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0); in he_init_cs_block()
596 he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1); in he_init_cs_block()
597 he_writel_mbox(he_dev, 0x14585, CS_RTFWR); in he_init_cs_block()
599 he_writel_mbox(he_dev, 0x4680, CS_RTATR); in he_init_cs_block()
602 he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET); in he_init_cs_block()
603 he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX); in he_init_cs_block()
604 he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN); in he_init_cs_block()
605 he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC); in he_init_cs_block()
606 he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC); in he_init_cs_block()
607 he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL); in he_init_cs_block()
610 he_writel_mbox(he_dev, 0x5, CS_OTPPER); in he_init_cs_block()
611 he_writel_mbox(he_dev, 0x14, CS_OTWPER); in he_init_cs_block()
614 he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0); in he_init_cs_block()
615 he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1); in he_init_cs_block()
616 he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2); in he_init_cs_block()
617 he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3); in he_init_cs_block()
618 he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4); in he_init_cs_block()
621 he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0); in he_init_cs_block()
622 he_writel_mbox(he_dev, 0x4701, CS_ERCTL1); in he_init_cs_block()
623 he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2); in he_init_cs_block()
624 he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0); in he_init_cs_block()
625 he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1); in he_init_cs_block()
626 he_writel_mbox(he_dev, 0xf424, CS_RTFWR); in he_init_cs_block()
628 he_writel_mbox(he_dev, 0x4680, CS_RTATR); in he_init_cs_block()
631 he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET); in he_init_cs_block()
632 he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX); in he_init_cs_block()
633 he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN); in he_init_cs_block()
634 he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC); in he_init_cs_block()
635 he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC); in he_init_cs_block()
636 he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL); in he_init_cs_block()
639 he_writel_mbox(he_dev, 0x6, CS_OTPPER); in he_init_cs_block()
640 he_writel_mbox(he_dev, 0x1e, CS_OTWPER); in he_init_cs_block()
643 he_writel_mbox(he_dev, 0x8, CS_OTTLIM); in he_init_cs_block()
645 for (reg = 0; reg < 0x8; ++reg) in he_init_cs_block()
646 he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg); in he_init_cs_block()
666 for (reg = 0x0; reg < 0xff; ++reg) in he_init_cs_block_rcm()
667 he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg); in he_init_cs_block_rcm()
671 for (reg = 0x100; reg < 0x1ff; ++reg) in he_init_cs_block_rcm()
672 he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg); in he_init_cs_block_rcm()
692 for (j = 0; j < 16; j++) { in he_init_cs_block_rcm()
693 (*rategrid)[0][j] = rate; in he_init_cs_block_rcm()
698 for (j = 0; j < 16; j++) in he_init_cs_block_rcm()
712 rate_atmf = 0; in he_init_cs_block_rcm()
713 while (rate_atmf < 0x400) { in he_init_cs_block_rcm()
714 man = (rate_atmf & 0x1f) << 4; in he_init_cs_block_rcm()
726 for (i = 255; i > 0; i--) in he_init_cs_block_rcm()
751 buf = 0; in he_init_cs_block_rcm()
757 #define RTGTBL_OFFSET 0x400 in he_init_cs_block_rcm()
759 if (rate_atmf & 0x1) in he_init_cs_block_rcm()
767 return 0; in he_init_cs_block_rcm()
776 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32)); in he_init_group()
777 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32)); in he_init_group()
778 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32)); in he_init_group()
779 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_init_group()
800 CONFIG_RBPL_BUFSIZE, 64, 0); in he_init_group()
816 for (i = 0; i < CONFIG_RBPL_SIZE; ++i) { in he_init_group()
855 he_writel(he_dev, 0, G0_RBRQ_H + (group * 16)); in he_init_group()
864 he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1), in he_init_group()
880 he_writel(he_dev, 0, G0_TBRQ_H + (group * 16)); in he_init_group()
884 return 0; in he_init_group()
923 *he_dev->irq_tailoffset = 0; in he_init_irq()
927 for (i = 0; i < CONFIG_IRQ_SIZE; ++i) in he_init_irq()
935 he_writel(he_dev, 0x0, IRQ0_DATA); in he_init_irq()
937 he_writel(he_dev, 0x0, IRQ1_BASE); in he_init_irq()
938 he_writel(he_dev, 0x0, IRQ1_HEAD); in he_init_irq()
939 he_writel(he_dev, 0x0, IRQ1_CNTL); in he_init_irq()
940 he_writel(he_dev, 0x0, IRQ1_DATA); in he_init_irq()
942 he_writel(he_dev, 0x0, IRQ2_BASE); in he_init_irq()
943 he_writel(he_dev, 0x0, IRQ2_HEAD); in he_init_irq()
944 he_writel(he_dev, 0x0, IRQ2_CNTL); in he_init_irq()
945 he_writel(he_dev, 0x0, IRQ2_DATA); in he_init_irq()
947 he_writel(he_dev, 0x0, IRQ3_BASE); in he_init_irq()
948 he_writel(he_dev, 0x0, IRQ3_HEAD); in he_init_irq()
949 he_writel(he_dev, 0x0, IRQ3_CNTL); in he_init_irq()
950 he_writel(he_dev, 0x0, IRQ3_DATA); in he_init_irq()
954 he_writel(he_dev, 0x0, GRP_10_MAP); in he_init_irq()
955 he_writel(he_dev, 0x0, GRP_32_MAP); in he_init_irq()
956 he_writel(he_dev, 0x0, GRP_54_MAP); in he_init_irq()
957 he_writel(he_dev, 0x0, GRP_76_MAP); in he_init_irq()
967 return 0; in he_init_irq()
987 membase = pci_resource_start(pci_dev, 0); in he_start()
988 HPRINTK("membase = 0x%lx irq = %d.\n", membase, pci_dev->irq); in he_start()
995 if (pci_read_config_dword(pci_dev, GEN_CNTL_0, &gen_cntl_0) != 0) { in he_start()
1000 if (pci_write_config_dword(pci_dev, GEN_CNTL_0, gen_cntl_0) != 0) { in he_start()
1005 if (pci_read_config_word(pci_dev, PCI_COMMAND, &command) != 0) { in he_start()
1011 if (pci_write_config_word(pci_dev, PCI_COMMAND, command) != 0) { in he_start()
1054 he_writel(he_dev, 0x0, RESET_CNTL); in he_start()
1055 he_writel(he_dev, 0xff, RESET_CNTL); in he_start()
1059 if ((status & BOARD_RST_STATUS) == 0) { in he_start()
1082 for (i = 0; i < PROD_ID_LEN; ++i) in he_start()
1087 for (i = 0; i < 6; ++i) in he_start()
1091 he_dev->media & 0x40 ? "SM" : "MM", dev->esi); in he_start()
1110 he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL); in he_start()
1113 lb_swap |= SWAP_RNUM_MAX(0xf); in he_start()
1117 if ((err = he_init_irq(he_dev)) != 0) in he_start()
1139 * 0 ____________1023 bytes 0 _______________________2047 bytes in he_start()
1188 he_dev->r0_startrow = 0; in he_start()
1222 SLICE_X(0x2) | ARB_RNUM_MAX(0xf) | TH_PRTY(0x3) | in he_start()
1223 RH_PRTY(0x3) | TL_PRTY(0x2) | RL_PRTY(0x1) | in he_start()
1224 (he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) | in he_start()
1225 (he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)), in he_start()
1229 (he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)), in he_start()
1233 (he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) | in he_start()
1242 (he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) | in he_start()
1243 (he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) | in he_start()
1247 he_writel(he_dev, DRF_THRESH(0x20) | in he_start()
1248 (he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) | in he_start()
1252 he_writel(he_dev, 0x0, TXAAL5_PROTO); in he_start()
1260 for (i = 0; i < TCM_MEM_SIZE; ++i) in he_start()
1261 he_writel_tcm(he_dev, 0, i); in he_start()
1263 for (i = 0; i < RCM_MEM_SIZE; ++i) in he_start()
1264 he_writel_rcm(he_dev, 0, i); in he_start()
1270 * 0x0 ___________________ in he_start()
1276 * 0x8000|___________________| in he_start()
1279 * 0xc000|___________________| in he_start()
1282 * 0xe000|___________________| in he_start()
1284 * 0xf000|___________________| in he_start()
1286 * 0x10000|___________________| in he_start()
1292 * 0x1ffff|___________________| in he_start()
1307 * 0x0 ___________________ in he_start()
1313 * 0x8000|___________________| in he_start()
1319 * 0xd000|___________________| in he_start()
1322 * 0xe000|___________________| in he_start()
1328 * 0xffff|___________________| in he_start()
1331 he_writel(he_dev, 0x08000, RCMLBM_BA); in he_start()
1332 he_writel(he_dev, 0x0e000, RCMRSRB_BA); in he_start()
1333 he_writel(he_dev, 0x0d800, RCMABR_BA); in he_start()
1340 he_writel(he_dev, 0x0, RLBC_H); in he_start()
1341 he_writel(he_dev, 0x0, RLBC_T); in he_start()
1342 he_writel(he_dev, 0x0, RLBC_H2); in he_start()
1349 he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA); in he_start()
1354 he_writel(he_dev, 0x000f, G0_INMQ_S); in he_start()
1355 he_writel(he_dev, 0x200f, G0_INMQ_L); in he_start()
1357 he_writel(he_dev, 0x001f, G1_INMQ_S); in he_start()
1358 he_writel(he_dev, 0x201f, G1_INMQ_L); in he_start()
1360 he_writel(he_dev, 0x002f, G2_INMQ_S); in he_start()
1361 he_writel(he_dev, 0x202f, G2_INMQ_L); in he_start()
1363 he_writel(he_dev, 0x003f, G3_INMQ_S); in he_start()
1364 he_writel(he_dev, 0x203f, G3_INMQ_L); in he_start()
1366 he_writel(he_dev, 0x004f, G4_INMQ_S); in he_start()
1367 he_writel(he_dev, 0x204f, G4_INMQ_L); in he_start()
1369 he_writel(he_dev, 0x005f, G5_INMQ_S); in he_start()
1370 he_writel(he_dev, 0x205f, G5_INMQ_L); in he_start()
1372 he_writel(he_dev, 0x006f, G6_INMQ_S); in he_start()
1373 he_writel(he_dev, 0x206f, G6_INMQ_L); in he_start()
1375 he_writel(he_dev, 0x007f, G7_INMQ_S); in he_start()
1376 he_writel(he_dev, 0x207f, G7_INMQ_L); in he_start()
1378 he_writel(he_dev, 0x0000, G0_INMQ_S); in he_start()
1379 he_writel(he_dev, 0x0008, G0_INMQ_L); in he_start()
1381 he_writel(he_dev, 0x0001, G1_INMQ_S); in he_start()
1382 he_writel(he_dev, 0x0009, G1_INMQ_L); in he_start()
1384 he_writel(he_dev, 0x0002, G2_INMQ_S); in he_start()
1385 he_writel(he_dev, 0x000a, G2_INMQ_L); in he_start()
1387 he_writel(he_dev, 0x0003, G3_INMQ_S); in he_start()
1388 he_writel(he_dev, 0x000b, G3_INMQ_L); in he_start()
1390 he_writel(he_dev, 0x0004, G4_INMQ_S); in he_start()
1391 he_writel(he_dev, 0x000c, G4_INMQ_L); in he_start()
1393 he_writel(he_dev, 0x0005, G5_INMQ_S); in he_start()
1394 he_writel(he_dev, 0x000d, G5_INMQ_L); in he_start()
1396 he_writel(he_dev, 0x0006, G6_INMQ_S); in he_start()
1397 he_writel(he_dev, 0x000e, G6_INMQ_L); in he_start()
1399 he_writel(he_dev, 0x0007, G7_INMQ_S); in he_start()
1400 he_writel(he_dev, 0x000f, G7_INMQ_L); in he_start()
1405 he_writel(he_dev, 0x0, MCC); in he_start()
1406 he_writel(he_dev, 0x0, OEC); in he_start()
1407 he_writel(he_dev, 0x0, DCC); in he_start()
1408 he_writel(he_dev, 0x0, CEC); in he_start()
1416 if (he_init_cs_block_rcm(he_dev) < 0) in he_start()
1424 sizeof(struct he_tpd), TPD_ALIGNMENT, 0); in he_start()
1432 if (he_init_group(he_dev, 0) != 0) in he_start()
1436 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32)); in he_start()
1437 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32)); in he_start()
1438 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32)); in he_start()
1439 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_start()
1442 he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32)); in he_start()
1443 he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32)); in he_start()
1444 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_start()
1446 he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32)); in he_start()
1448 he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16)); in he_start()
1449 he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16)); in he_start()
1450 he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0), in he_start()
1452 he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16)); in he_start()
1454 he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16)); in he_start()
1455 he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16)); in he_start()
1456 he_writel(he_dev, TBRQ_THRESH(0x1), in he_start()
1458 he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16)); in he_start()
1501 for (i = 0; i < HE_NUM_CS_STPER; ++i) { in he_start()
1502 he_dev->cs_stper[i].inuse = 0; in he_start()
1505 he_dev->total_bw = 0; in he_start()
1513 he_dev->irq_peak = 0; in he_start()
1514 he_dev->rbrq_peak = 0; in he_start()
1515 he_dev->rbpl_peak = 0; in he_start()
1516 he_dev->tbrq_peak = 0; in he_start()
1520 return 0; in he_start()
1616 tpd->reserved = 0; in __alloc_tpd()
1617 tpd->iovec[0].addr = 0; tpd->iovec[0].len = 0; in __alloc_tpd()
1618 tpd->iovec[1].addr = 0; tpd->iovec[1].len = 0; in __alloc_tpd()
1619 tpd->iovec[2].addr = 0; tpd->iovec[2].len = 0; in __alloc_tpd()
1650 int pdus_assembled = 0; in he_service_rbrq()
1651 int updated = 0; in he_service_rbrq()
1657 HPRINTK("%p rbrq%d 0x%x len=%d cid=0x%x %s%s%s%s%s%s\n", in he_service_rbrq()
1678 hprintk("vcc/he_vcc == NULL (cid 0x%x)\n", cid); in he_service_rbrq()
1689 hprintk("HBUF_ERR! (cid 0x%x)\n", cid); in he_service_rbrq()
1701 HPRINTK("wake_up rx_waitq (cid 0x%x)\n", cid); in he_service_rbrq()
1728 if (rx_skb_reserve > 0) in he_service_rbrq()
1748 if (vcc->vpi == 0 && vcc->vci >= ATM_NOT_RSV_VCI) { in he_service_rbrq()
1759 …hprintk("pdu_len (%d) > vcc->qos.rxtp.max_sdu (%d)! cid 0x%x\n", skb->len, vcc->qos.rxtp.max_sdu,… in he_service_rbrq()
1777 he_vcc->pdu_len = 0; in he_service_rbrq()
1805 int slot, updated = 0; in he_service_tbrq()
1813 HPRINTK("tbrq%d 0x%x%s%s\n", in he_service_tbrq()
1834 HPRINTK("wake_up(tx_waitq) cid 0x%x\n", in he_service_tbrq()
1842 for (slot = 0; slot < TPD_MAXIOV; ++slot) { in he_service_tbrq()
1885 int moved = 0; in he_service_rbpl()
1930 int updated = 0; in he_tasklet()
1932 HPRINTK("tasklet (0x%lx)\n", data); in he_tasklet()
1976 hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR)); in he_tasklet()
1983 HPRINTK("isw not updated 0x%x\n", he_dev->irq_head->isw); in he_tasklet()
1985 he_service_rbrq(he_dev, 0); in he_tasklet()
1986 he_service_rbpl(he_dev, 0); in he_tasklet()
1987 he_service_tbrq(he_dev, 0); in he_tasklet()
1990 hprintk("bad isw 0x%x?\n", he_dev->irq_head->isw); in he_tasklet()
2016 int handled = 0; in he_irq_handler()
2054 HPRINTK("tpdrq %p cid 0x%x -> tpdrq_tail %p\n", in __enqueue_tpd()
2076 hprintk("tpdrq full (cid 0x%x)\n", cid); in __enqueue_tpd()
2083 for (slot = 0; slot < TPD_MAXIOV; ++slot) { in __enqueue_tpd()
2120 int err = 0; in he_open()
2126 return 0; in he_open()
2141 he_vcc->pdu_len = 0; in he_open()
2153 if (pcr_goal == 0) in he_open()
2155 if (pcr_goal < 0) /* means round down, technically */ in he_open()
2158 HPRINTK("open tx cid 0x%x pcr_goal %d\n", cid, pcr_goal); in he_open()
2178 if (TSR0_CONN_STATE(tsr0) != 0) { in he_open()
2179 hprintk("cid 0x%x not idle (tsr0 = 0x%x)\n", cid, tsr0); in he_open()
2188 tsr0 = TSR0_UBR | TSR0_GROUP(0) | tsr0_aal | in he_open()
2206 for (reg = 0; reg < HE_NUM_CS_STPER; ++reg) in he_open()
2207 if (he_dev->cs_stper[reg].inuse == 0 || in he_open()
2233 tsr0 = TSR0_CBR | TSR0_GROUP(0) | tsr0_aal | in he_open()
2246 he_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) | in he_open()
2251 he_writel_tsr3(he_dev, 0x0, cid); in he_open()
2252 he_writel_tsr5(he_dev, 0x0, cid); in he_open()
2253 he_writel_tsr6(he_dev, 0x0, cid); in he_open()
2254 he_writel_tsr7(he_dev, 0x0, cid); in he_open()
2255 he_writel_tsr8(he_dev, 0x0, cid); in he_open()
2256 he_writel_tsr10(he_dev, 0x0, cid); in he_open()
2257 he_writel_tsr11(he_dev, 0x0, cid); in he_open()
2258 he_writel_tsr12(he_dev, 0x0, cid); in he_open()
2259 he_writel_tsr13(he_dev, 0x0, cid); in he_open()
2260 he_writel_tsr14(he_dev, 0x0, cid); in he_open()
2268 HPRINTK("open rx cid 0x%x (rx_waitq %p)\n", cid, in he_open()
2289 hprintk("cid 0x%x not idle (rsr0 = 0x%x)\n", cid, rsr0); in he_open()
2294 rsr1 = RSR1_GROUP(0) | RSR1_RBPL_ONLY; in he_open()
2295 rsr4 = RSR4_GROUP(0) | RSR4_RBPL_ONLY; in he_open()
2297 (RSR0_EPD_ENABLE|RSR0_PPD_ENABLE) : 0; in he_open()
2300 if (vpi == 0 && vci >= ATM_NOT_RSV_VCI) in he_open()
2337 int retry = 0, sleep = 1, tx_inuse; in he_close()
2347 HPRINTK("close rx cid 0x%x\n", cid); in he_close()
2355 HPRINTK("close cid 0x%x RCC_BUSY\n", cid); in he_close()
2372 if (timeout == 0) in he_close()
2373 hprintk("close rx timeout cid 0x%x\n", cid); in he_close()
2375 HPRINTK("close rx cid 0x%x complete\n", cid); in he_close()
2383 HPRINTK("close tx cid 0x%x\n", cid); in he_close()
2404 hprintk("close tx cid 0x%x tx_inuse = %d\n", cid, tx_inuse); in he_close()
2416 | TSR1_PCR(0), cid); in he_close()
2426 hprintk("close tx he_alloc_tpd failed cid 0x%x\n", cid); in he_close()
2446 if (timeout == 0) { in he_close()
2447 hprintk("close tx timeout cid 0x%x\n", cid); in he_close()
2452 HPRINTK("close tx cid 0x%x !TSR4_SESSION_ENDED (tsr4 = 0x%x)\n", cid, tsr4); in he_close()
2456 while (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) { in he_close()
2457 HPRINTK("close tx cid 0x%x TSR0_CONN_STATE != 0 (tsr0 = 0x%x)\n", cid, tsr0); in he_close()
2468 if (he_dev->cs_stper[reg].inuse == 0) in he_close()
2469 hprintk("cs_stper[%d].inuse = 0!\n", reg); in he_close()
2477 HPRINTK("close tx cid 0x%x complete\n", cid); in he_close()
2493 int i, slot = 0; in he_send()
2496 #define HE_TPD_BUFSIZE 0xffff in he_send()
2556 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in he_send()
2577 slot = 0; in he_send()
2581 frag, 0, skb_frag_size(frag), DMA_TO_DEVICE); in he_send()
2604 return 0; in he_send()
2613 int err = 0; in he_ioctl()
2651 if (err == 0) in he_ioctl()
2675 HPRINTK("phy_put(val 0x%x, addr 0x%lx)\n", val, addr); in he_phy_put()
2695 HPRINTK("phy_get(addr 0x%lx) =0x%x\n", addr, reg); in he_phy_get()
2710 static long mcc = 0, oec = 0, dcc = 0, cec = 0; in he_proc_read()
2719 he_dev->prod_id, he_dev->media & 0x40 ? "SM" : "MM"); in he_proc_read()
2757 if (inuse < 0) in he_proc_read()
2769 for (i = 0; i < HE_NUM_CS_STPER; ++i) in he_proc_read()
2779 return 0; in he_proc_read()
2786 u32 val = 0, tmp_read = 0; in read_prom_byte()
2787 int i, j = 0; in read_prom_byte()
2788 u8 byte_read = 0; in read_prom_byte()
2791 val &= 0xFFFFE0FF; in read_prom_byte()
2794 val |= 0x800; in read_prom_byte()
2798 for (i = 0; i < ARRAY_SIZE(readtab); i++) { in read_prom_byte()
2804 for (i = 7; i >= 0; i--) { in read_prom_byte()
2811 j = 0; in read_prom_byte()
2813 val &= 0xFFFFF7FF; /* Turn off write enable */ in read_prom_byte()
2817 for (i = 7; i >= 0; i--) { in read_prom_byte()
2836 module_param(disable64, bool, 0);
2838 module_param(nvpibits, short, 0);
2839 MODULE_PARM_DESC(nvpibits, "numbers of bits for vpi (default 0)");
2840 module_param(nvcibits, short, 0);
2842 module_param(rx_skb_reserve, short, 0);
2844 module_param(irq_coalesce, bool, 0);
2846 module_param(sdh, bool, 0);
2847 MODULE_PARM_DESC(sdh, "use SDH framing (default 0)");
2850 { PCI_VDEVICE(FORE, PCI_DEVICE_ID_FORE_HE), 0 },
2851 { 0, }