22 #define ATAPI_CONTROL1_REG		0x180
23 #define ATAPI_STATUS_REG		0x184
24 #define ATAPI_INT_ENABLE_REG		0x188
25 #define ATAPI_DTB_ADR_REG		0x198
26 #define ATAPI_DMA_START_ADR_REG		0x19C
27 #define ATAPI_DMA_TRANS_CNT_REG		0x1A0
28 #define ATAPI_CONTROL2_REG		0x1A4
29 #define ATAPI_SIG_ST_REG		0x1B0
30 #define ATAPI_BYTE_SWAP_REG		0x1BC
39 #define ATAPI_CONTROL1_START		BIT(0)
48 #define ATAPI_STATUS_ACT		BIT(0)
57 #define ATAPI_INT_ENABLE_ACT		BIT(0)
60 #define SATAPHYADDR_REG			0x200
61 #define SATAPHYWDATA_REG		0x204
62 #define SATAPHYACCEN_REG		0x208
63 #define SATAPHYRESET_REG		0x20C
64 #define SATAPHYRDATA_REG		0x210
65 #define SATAPHYACK_REG			0x214
73 #define SATAPHYACCEN_PHYLANE		BIT(0)
77 #define SATAPHYRESET_PHYSRES		BIT(0)
80 #define SATAPHYACK_PHYACK		BIT(0)
83 #define BISTCONF_REG			0x102C
84 #define SDATA_REG			0x1100
85 #define SSDEVCON_REG			0x1204
87 #define SCRSSTS_REG			0x1400
88 #define SCRSERR_REG			0x1404
89 #define SCRSCON_REG			0x1408
90 #define SCRSACT_REG			0x140C
92 #define SATAINTSTAT_REG			0x1508
93 #define SATAINTMASK_REG			0x150C
97 #define SATAINTSTAT_ATA			BIT(0)
103 #define SATAINTMASK_ATAMSK		BIT(0)
104 #define SATAINTMASK_ALL_GEN1		0x7ff
105 #define SATAINTMASK_ALL_GEN2		0xfff
111 #define SATAPCTLR1_REG			0x43
112 #define SATAPCTLR2_REG			0x52
113 #define SATAPCTLR3_REG			0x5A
114 #define SATAPCTLR4_REG			0x60
116 /* Descriptor table word 0 bit (when DTA32M = 1) */
117 #define SATA_RCAR_DTEND			BIT(0)
119 #define SATA_RCAR_DMA_BOUNDARY		0x1FFFFFFFUL
122 #define RCAR_GEN2_PHY_CTL1_REG		0x1704
123 #define RCAR_GEN2_PHY_CTL1		0x34180002
124 #define RCAR_GEN2_PHY_CTL1_SS		0xC180	/* Spread Spectrum */
126 #define RCAR_GEN2_PHY_CTL2_REG		0x170C
127 #define RCAR_GEN2_PHY_CTL2		0x00002303
129 #define RCAR_GEN2_PHY_CTL3_REG		0x171C
130 #define RCAR_GEN2_PHY_CTL3		0x000B0194
132 #define RCAR_GEN2_PHY_CTL4_REG		0x1724
133 #define RCAR_GEN2_PHY_CTL4		0x00030994
135 #define RCAR_GEN2_PHY_CTL5_REG		0x1740
136 #define RCAR_GEN2_PHY_CTL5		0x03004001
158 	iowrite32(0, base + SATAPHYADDR_REG);  in sata_rcar_gen1_phy_preinit()
163 	iowrite32(0, base + SATAPHYRESET_REG);  in sata_rcar_gen1_phy_preinit()
173 	iowrite32(0, base + SATAPHYRESET_REG);  in sata_rcar_gen1_phy_write()
184 	for (timeout = 0; timeout < 100; timeout++) {  in sata_rcar_gen1_phy_write()
192 	iowrite32(0, base + SATAPHYADDR_REG);  in sata_rcar_gen1_phy_write()
198 	sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);  in sata_rcar_gen1_phy_init()
199 	sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);  in sata_rcar_gen1_phy_init()
200 	sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);  in sata_rcar_gen1_phy_init()
201 	sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);  in sata_rcar_gen1_phy_init()
202 	sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);  in sata_rcar_gen1_phy_init()
203 	sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);  in sata_rcar_gen1_phy_init()
289 	iowrite32(0x55, ioaddr->nsect_addr);  in sata_rcar_ata_devchk()
290 	iowrite32(0xaa, ioaddr->lbal_addr);  in sata_rcar_ata_devchk()
292 	iowrite32(0xaa, ioaddr->nsect_addr);  in sata_rcar_ata_devchk()
293 	iowrite32(0x55, ioaddr->lbal_addr);  in sata_rcar_ata_devchk()
295 	iowrite32(0x55, ioaddr->nsect_addr);  in sata_rcar_ata_devchk()
296 	iowrite32(0xaa, ioaddr->lbal_addr);  in sata_rcar_ata_devchk()
301 	if (nsect == 0x55 && lbal == 0xaa)  in sata_rcar_ata_devchk()
337 	unsigned int devmask = 0;  in sata_rcar_softreset()
341 	/* determine if device 0 is present */  in sata_rcar_softreset()
342 	if (sata_rcar_ata_devchk(ap, 0))  in sata_rcar_softreset()
343 		devmask |= 1 << 0;  in sata_rcar_softreset()
354 	classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);  in sata_rcar_softreset()
356 	return 0;  in sata_rcar_softreset()
439 	if (unlikely(buflen & 0x01)) {  in sata_rcar_data_xfer()
451 			*buf = pad[0];  in sata_rcar_data_xfer()
453 			pad[0] = *buf;  in sata_rcar_data_xfer()
473 	for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&  in sata_rcar_drain_fifo()
488 	return 0;  in sata_rcar_scr_read()
498 	return 0;  in sata_rcar_scr_write()
592 	/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */  in sata_rcar_bmdma_stop()
599 	u8 host_stat = 0;  in sata_rcar_bmdma_status()
654 	int freeze = 0;  in sata_rcar_serr_interrupt()
661 	ata_port_dbg(ap, "SError @host_intr: 0x%x\n", serror);  in sata_rcar_serr_interrupt()
671 		freeze = serror & SERR_COMM_WAKE ? 0 : 1;  in sata_rcar_serr_interrupt()
684 	int handled = 0;  in sata_rcar_ata_interrupt()
700 	unsigned int handled = 0;  in sata_rcar_interrupt()
714 	ap = host->ports[0];  in sata_rcar_interrupt()
731 	struct ata_port *ap = host->ports[0];  in sata_rcar_setup_port()
771 	/* ISM mode, PRD mode, DTEND flag at bit 0 */  in sata_rcar_init_module()
784 	iowrite32(0, base + SATAINTSTAT_REG);  in sata_rcar_init_module()
866 	irq = platform_get_irq(pdev, 0);  in sata_rcar_probe()
867 	if (irq < 0)  in sata_rcar_probe()
878 	if (ret < 0)  in sata_rcar_probe()
889 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in sata_rcar_probe()
901 	ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,  in sata_rcar_probe()
904 		return 0;  in sata_rcar_probe()
921 	iowrite32(0, base + ATAPI_INT_ENABLE_REG);  in sata_rcar_remove()
923 	iowrite32(0, base + SATAINTSTAT_REG);  in sata_rcar_remove()
940 	iowrite32(0, base + ATAPI_INT_ENABLE_REG);  in sata_rcar_suspend()
946 	return 0;  in sata_rcar_suspend()
957 	if (ret < 0) {  in sata_rcar_resume()
966 		iowrite32(0, base + SATAINTSTAT_REG);  in sata_rcar_resume()
976 	return 0;  in sata_rcar_resume()
985 	if (ret < 0) {  in sata_rcar_restore()
997 	return 0;  in sata_rcar_restore()