Lines Matching +full:0 +full:x00000ff0
56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */
58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
60 { 0, }
65 const struct sis_laptop *lap = &sis_laptop[0]; in sis_short_ata40()
75 return 0; in sis_short_ata40()
88 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); in sis_old_port_base()
103 int port = 0x40; in sis_port_base()
106 /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */ in sis_port_base()
107 pci_read_config_dword(pdev, 0x54, ®54); in sis_port_base()
108 if (reg54 & 0x40000000) in sis_port_base()
109 port = 0x70; in sis_port_base()
128 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); in sis_133_cable_detect()
129 if ((tmp & 0x8000) && !sis_short_ata40(pdev)) in sis_133_cable_detect()
147 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ in sis_66_cable_detect()
148 pci_read_config_byte(pdev, 0x48, &tmp); in sis_66_cable_detect()
150 if ((tmp & 0x10) && !sis_short_ata40(pdev)) in sis_66_cable_detect()
167 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ in sis_pre_reset()
168 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ in sis_pre_reset()
179 pci_write_config_byte(pdev, 0x4B, 0); in sis_pre_reset()
198 u8 mask = 0x11; in sis_set_fifo()
204 pci_read_config_byte(pdev, 0x4B, &fifoctrl); in sis_set_fifo()
210 pci_write_config_byte(pdev, 0x4B, fifoctrl); in sis_set_fifo()
233 static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; in sis_old_set_piomode()
234 static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; in sis_old_set_piomode()
241 t1 &= ~0x0F; /* Clear active/recovery timings */ in sis_old_set_piomode()
242 t2 &= ~0x07; in sis_old_set_piomode()
269 static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; in sis_100_set_piomode()
296 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ in sis_133_set_piomode()
297 0x0C266000, in sis_133_set_piomode()
298 0x04263000, in sis_133_set_piomode()
299 0x0C0A3000, in sis_133_set_piomode()
300 0x05093000 in sis_133_set_piomode()
303 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ in sis_133_set_piomode()
304 0x091C4000, in sis_133_set_piomode()
305 0x031C2000, in sis_133_set_piomode()
306 0x09072000, in sis_133_set_piomode()
307 0x04062000 in sis_133_set_piomode()
314 t1 &= 0xC0C00FFF; /* Mask out timing */ in sis_133_set_piomode()
316 if (t1 & 0x08) /* 100 or 133 ? */ in sis_133_set_piomode()
343 static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; in sis_old_set_dmamode()
344 static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; in sis_old_set_dmamode()
349 /* bits 3-0 hold recovery timing bits 8-10 active timing and in sis_old_set_dmamode()
351 timing &= ~0x870F; in sis_old_set_dmamode()
356 timing &= ~0x6000; in sis_old_set_dmamode()
382 /* MWDMA 0-2 and UDMA 0-5 */ in sis_66_set_dmamode()
383 static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; in sis_66_set_dmamode()
384 static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; in sis_66_set_dmamode()
389 /* bits 3-0 hold recovery timing bits 8-10 active timing and in sis_66_set_dmamode()
391 timing &= ~0x870F; in sis_66_set_dmamode()
396 timing &= ~0xF000; in sis_66_set_dmamode()
421 static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; in sis_100_set_dmamode()
428 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ in sis_100_set_dmamode()
430 timing &= ~0x8F; in sis_100_set_dmamode()
455 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; in sis_133_early_set_dmamode()
462 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ in sis_133_early_set_dmamode()
464 timing &= ~0x8F; in sis_133_early_set_dmamode()
492 static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 }; in sis_133_set_dmamode()
493 static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 }; in sis_133_set_dmamode()
496 t1 &= 0xC0C00FFF; in sis_133_set_dmamode()
498 t1 &= ~0x00000004; in sis_133_set_dmamode()
499 if (t1 & 0x08) in sis_133_set_dmamode()
505 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; in sis_133_set_dmamode()
506 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; in sis_133_set_dmamode()
509 t1 &= ~0x00000FF0; in sis_133_set_dmamode()
511 t1 |= 0x00000004; in sis_133_set_dmamode()
512 if (t1 & 0x08) in sis_133_set_dmamode()
537 if (!(t1 & 0x08)) in sis_133_mode_filter()
538 mask &= ~(0xC0 << ATA_SHIFT_UDMA); in sis_133_mode_filter()
660 pci_read_config_word(pdev, 0x50, ®w); in sis_fixup()
661 if (regw & 0x08) in sis_fixup()
662 pci_write_config_word(pdev, 0x50, regw & ~0x08); in sis_fixup()
663 pci_read_config_word(pdev, 0x52, ®w); in sis_fixup()
664 if (regw & 0x08) in sis_fixup()
665 pci_write_config_word(pdev, 0x52, regw & ~0x08); in sis_fixup()
671 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); in sis_fixup()
673 pci_read_config_byte(pdev, 0x49, ®); in sis_fixup()
674 if (!(reg & 0x01)) in sis_fixup()
675 pci_write_config_byte(pdev, 0x49, reg | 0x01); in sis_fixup()
681 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); in sis_fixup()
683 pci_read_config_byte(pdev, 0x52, ®); in sis_fixup()
684 if (!(reg & 0x04)) in sis_fixup()
685 pci_write_config_byte(pdev, 0x52, reg | 0x04); in sis_fixup()
691 if (( reg & 0x0F ) != 0x00) in sis_fixup()
692 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); in sis_fixup()
699 pci_read_config_byte(pdev, 0x52, ®); in sis_fixup()
700 if (!(reg & 0x08)) in sis_fixup()
701 pci_write_config_byte(pdev, 0x52, reg|0x08); in sis_fixup()
733 { 0x0968, &sis_info133 }, in sis_init_one()
734 { 0x0966, &sis_info133 }, in sis_init_one()
735 { 0x0965, &sis_info133 }, in sis_init_one()
736 { 0x0745, &sis_info100 }, in sis_init_one()
737 { 0x0735, &sis_info100 }, in sis_init_one()
738 { 0x0733, &sis_info100 }, in sis_init_one()
739 { 0x0635, &sis_info100 }, in sis_init_one()
740 { 0x0633, &sis_info100 }, in sis_init_one()
742 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ in sis_init_one()
743 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ in sis_init_one()
745 { 0x0640, &sis_info66 }, in sis_init_one()
746 { 0x0630, &sis_info66 }, in sis_init_one()
747 { 0x0620, &sis_info66 }, in sis_init_one()
748 { 0x0540, &sis_info66 }, in sis_init_one()
749 { 0x0530, &sis_info66 }, in sis_init_one()
751 { 0x5600, &sis_info33 }, in sis_init_one()
752 { 0x5598, &sis_info33 }, in sis_init_one()
753 { 0x5597, &sis_info33 }, in sis_init_one()
754 { 0x5591, &sis_info33 }, in sis_init_one()
755 { 0x5582, &sis_info33 }, in sis_init_one()
756 { 0x5581, &sis_info33 }, in sis_init_one()
758 { 0x5596, &sis_info }, in sis_init_one()
759 { 0x5571, &sis_info }, in sis_init_one()
760 { 0x5517, &sis_info }, in sis_init_one()
761 { 0x5511, &sis_info }, in sis_init_one()
763 {0} in sis_init_one()
766 0x0, &sis_info133_early in sis_init_one()
769 0x0, &sis_info133 in sis_init_one()
772 0x0, &sis_info100_early in sis_init_one()
775 0x0, &sis_info100 in sis_init_one()
785 for (sets = &sis_chipsets[0]; sets->device; sets++) { in sis_init_one()
789 if (sets->device == 0x630) { /* SIS630 */ in sis_init_one()
790 if (host->revision >= 0x30) /* 630 ET */ in sis_init_one()
806 pci_read_config_dword(pdev, 0x54, &idemisc); in sis_init_one()
807 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); in sis_init_one()
809 pci_write_config_dword(pdev, 0x54, idemisc); in sis_init_one()
812 case 0x5518: /* SIS 962/963 */ in sis_init_one()
816 if ((idemisc & 0x40000000) == 0) { in sis_init_one()
817 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); in sis_init_one()
822 case 0x0180: /* SIS 965/965L */ in sis_init_one()
825 case 0x1180: /* SIS 966/966L */ in sis_init_one()
839 pci_read_config_byte(pdev, 0x4a, &idecfg); in sis_init_one()
840 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); in sis_init_one()
842 pci_write_config_byte(pdev, 0x4a, idecfg); in sis_init_one()
845 case 0x5517: in sis_init_one()
846 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ in sis_init_one()
849 pci_read_config_byte(pdev, 0x49, &prefctl); in sis_init_one()
852 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { in sis_init_one()
866 ppi[0] = chipset->info; in sis_init_one()
870 return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0); in sis_init_one()
886 return 0; in sis_reinit_one()
891 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
892 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
893 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */