Lines Matching +full:0 +full:x23
26 CY82_IDE_CMDREG = 0x04,
27 CY82_IDE_ADDRSETUP = 0x48,
28 CY82_IDE_MASTER_IOR = 0x4C,
29 CY82_IDE_MASTER_IOW = 0x4D,
30 CY82_IDE_SLAVE_IOR = 0x4E,
31 CY82_IDE_SLAVE_IOW = 0x4F,
32 CY82_IDE_MASTER_8BIT = 0x50,
33 CY82_IDE_SLAVE_8BIT = 0x51,
35 CY82_INDEX_PORT = 0x22,
36 CY82_DATA_PORT = 0x23,
38 CY82_INDEX_CTRLREG1 = 0x01,
39 CY82_INDEX_CHANNEL0 = 0x30,
40 CY82_INDEX_CHANNEL1 = 0x31,
41 CY82_INDEX_TIMEOUT = 0x32
45 module_param(enable_dma, bool, 0);
64 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) { in cy82c693_set_piomode()
69 time_16 = clamp_val(t.recover - 1, 0, 15) | in cy82c693_set_piomode()
70 (clamp_val(t.active - 1, 0, 15) << 4); in cy82c693_set_piomode()
71 time_8 = clamp_val(t.act8b - 1, 0, 15) | in cy82c693_set_piomode()
72 (clamp_val(t.rec8b - 1, 0, 15) << 4); in cy82c693_set_piomode()
74 if (adev->devno == 0) { in cy82c693_set_piomode()
77 addr &= ~0x0F; /* Mask bits */ in cy82c693_set_piomode()
78 addr |= clamp_val(t.setup - 1, 0, 15); in cy82c693_set_piomode()
87 addr &= ~0xF0; /* Mask bits */ in cy82c693_set_piomode()
88 addr |= (clamp_val(t.setup - 1, 0, 15) << 4); in cy82c693_set_piomode()
110 outb(reg, 0x22); in cy82c693_set_dmamode()
111 outb(adev->dma_mode - XFER_MW_DMA_0, 0x23); in cy82c693_set_dmamode()
113 /* 0x50 gives the best behaviour on the Alpha's using this chip */ in cy82c693_set_dmamode()
114 outb(CY82_INDEX_TIMEOUT, 0x22); in cy82c693_set_dmamode()
115 outb(0x50, 0x23); in cy82c693_set_dmamode()
147 return ata_pci_bmdma_init_one(pdev, ppi, &cy82c693_sht, NULL, 0); in cy82c693_init_one()