Lines Matching +full:sata +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ata_piix.c - Intel PATA/SATA controllers
6 * Please ALWAYS copy linux-[email protected]
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
14 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
15 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
19 * as Documentation/driver-api/libata.rst
32 * change little except in gaining more modes until SATA arrives. This
34 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
40 * PIIX4 errata #9 - Only on ultra obscure hw
41 * ICH3 errata #13 - Not observed to affect real hw
45 * PIIX4 errata #10 - BM IDE hang with non UDMA
47 * 440MX errata #15 - As PIIX4 errata #10
48 * PIIX4 errata #15 - Must not read control registers
50 * 440MX errata #13 - As PIIX4 errata #15
51 * ICH2 errata #21 - DMA mode 0 doesn't work right
52 * ICH0/1 errata #55 - As ICH2 errata #21
53 * ICH2 spec c #9 - Extra operations needed to handle
55 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
57 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
58 * ICH7 errata #16 - MWDMA1 timings are incorrect
61 * 450NX: errata #19 - DMA hangs on old 450NX
62 * 450NX: errata #20 - DMA hangs on old 450NX
63 * 450NX: errata #25 - Corruption with DMA on old 450NX
64 * ICH3 errata #15 - IDE deadlock under high load
65 * (BIOS must set dev 31 fn 0 bit 23)
66 * ICH3 errata #18 - Don't use native mode
86 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
87 ICH5_PMR = 0x90, /* address map register */
88 ICH5_PCS = 0x92, /* port control and status */
91 PIIX_SIDPR_IDX = 0,
95 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
106 P0 = 0, /* port 0 */
110 IDE = -1, /* IDE */
111 NA = -2, /* not available */
112 RV = -3, /* reserved */
116 /* host->flags bits */
157 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
159 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
162 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
164 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
166 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
168 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
170 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
172 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
174 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
176 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
178 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
180 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
181 /* Intel ICH4-L */
182 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
184 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
185 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* C-ICH (i810E2) */
189 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* ICH7/7-R (i945, i975) UDMA 100*/
195 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
196 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
198 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* SATA ports */
203 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
205 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
207 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
209 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
211 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
213 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
214 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
216 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
217 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
219 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
221 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
223 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
224 /* SATA Controller 1 IDE (ICH8) */
225 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
226 /* SATA Controller 2 IDE (ICH8) */
227 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
228 /* Mobile SATA Controller IDE (ICH8M), Apple */
229 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
230 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
231 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
232 /* Mobile SATA Controller IDE (ICH8M) */
233 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
234 /* SATA Controller IDE (ICH9) */
235 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
236 /* SATA Controller IDE (ICH9) */
237 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
238 /* SATA Controller IDE (ICH9) */
239 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
240 /* SATA Controller IDE (ICH9M) */
241 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
242 /* SATA Controller IDE (ICH9M) */
243 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
244 /* SATA Controller IDE (ICH9M) */
245 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
246 /* SATA Controller IDE (Tolapai) */
247 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
248 /* SATA Controller IDE (ICH10) */
249 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
250 /* SATA Controller IDE (ICH10) */
251 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* SATA Controller IDE (ICH10) */
253 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
254 /* SATA Controller IDE (ICH10) */
255 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* SATA Controller IDE (PCH) */
257 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
258 /* SATA Controller IDE (PCH) */
259 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
260 /* SATA Controller IDE (PCH) */
261 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
262 /* SATA Controller IDE (PCH) */
263 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller IDE (PCH) */
265 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (PCH) */
267 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
268 /* SATA Controller IDE (CPT) */
269 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
270 /* SATA Controller IDE (CPT) */
271 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
272 /* SATA Controller IDE (CPT) */
273 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (CPT) */
275 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (PBG) */
277 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
278 /* SATA Controller IDE (PBG) */
279 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (Panther Point) */
281 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
282 /* SATA Controller IDE (Panther Point) */
283 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
284 /* SATA Controller IDE (Panther Point) */
285 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
286 /* SATA Controller IDE (Panther Point) */
287 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (Lynx Point) */
289 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
290 /* SATA Controller IDE (Lynx Point) */
291 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
292 /* SATA Controller IDE (Lynx Point) */
293 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
294 /* SATA Controller IDE (Lynx Point) */
295 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
296 /* SATA Controller IDE (Lynx Point-LP) */
297 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
298 /* SATA Controller IDE (Lynx Point-LP) */
299 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
300 /* SATA Controller IDE (Lynx Point-LP) */
301 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (Lynx Point-LP) */
303 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
304 /* SATA Controller IDE (DH89xxCC) */
305 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
306 /* SATA Controller IDE (Avoton) */
307 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
308 /* SATA Controller IDE (Avoton) */
309 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
310 /* SATA Controller IDE (Avoton) */
311 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
312 /* SATA Controller IDE (Avoton) */
313 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
314 /* SATA Controller IDE (Wellsburg) */
315 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
316 /* SATA Controller IDE (Wellsburg) */
317 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
318 /* SATA Controller IDE (Wellsburg) */
319 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
320 /* SATA Controller IDE (Wellsburg) */
321 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
322 /* SATA Controller IDE (BayTrail) */
323 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
324 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
325 /* SATA Controller IDE (Coleto Creek) */
326 { 0x8086, 0x23a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
327 /* SATA Controller IDE (9 Series) */
328 { 0x8086, 0x8c88, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
329 /* SATA Controller IDE (9 Series) */
330 { 0x8086, 0x8c89, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_snb },
331 /* SATA Controller IDE (9 Series) */
332 { 0x8086, 0x8c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
333 /* SATA Controller IDE (9 Series) */
334 { 0x8086, 0x8c81, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
340 .mask = 0x7,
341 .port_enable = 0x3,
356 .mask = 0x3,
357 .port_enable = 0xf,
368 .mask = 0x3,
369 .port_enable = 0x5,
385 .mask = 0x3,
386 .port_enable = 0xf,
397 .mask = 0x3,
398 .port_enable = 0x3,
409 .mask = 0x3,
410 .port_enable = 0x1,
421 .mask = 0x3,
422 .port_enable = 0x3,
446 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
447 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
451 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
468 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
469 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
470 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
471 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
472 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
473 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
474 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
475 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
476 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
477 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
478 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
479 { 0x24CA, 0x10CF, 0x11AB }, /* ICH4M on Fujitsu-Siemens Lifebook S6120 */
480 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
481 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
482 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
484 { 0, }
489 if (!(ap->flags & PIIX_FLAG_PIO16)) in piix_port_start()
490 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; in piix_port_start()
496 * ich_pata_cable_detect - Probe host controller cable detect info
508 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in ich_pata_cable_detect()
509 struct piix_host_priv *hpriv = ap->host->private_data; in ich_pata_cable_detect()
510 const struct ich_laptop *lap = &ich_laptop[0]; in ich_pata_cable_detect()
514 while (lap->device) { in ich_pata_cable_detect()
515 if (lap->device == pdev->device && in ich_pata_cable_detect()
516 lap->subvendor == pdev->subsystem_vendor && in ich_pata_cable_detect()
517 lap->subdevice == pdev->subsystem_device) in ich_pata_cable_detect()
524 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; in ich_pata_cable_detect()
525 if ((hpriv->saved_iocfg & mask) == 0) in ich_pata_cable_detect()
531 * piix_pata_prereset - prereset for PATA host controller
540 struct ata_port *ap = link->ap; in piix_pata_prereset()
541 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in piix_pata_prereset()
543 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) in piix_pata_prereset()
544 return -ENOENT; in piix_pata_prereset()
553 struct pci_dev *dev = to_pci_dev(ap->host->dev); in piix_set_timings()
555 unsigned int is_slave = (adev->devno != 0); in piix_set_timings()
556 unsigned int master_port= ap->port_no ? 0x42 : 0x40; in piix_set_timings()
557 unsigned int slave_port = 0x44; in piix_set_timings()
561 int control = 0; in piix_set_timings()
564 * See Intel Document 298600-004 for the timing programing rules in piix_set_timings()
569 u8 timings[][2] = { { 0, 0 }, in piix_set_timings()
570 { 0, 0 }, in piix_set_timings()
571 { 1, 0 }, in piix_set_timings()
580 if (adev->class == ATA_DEV_ATA) in piix_set_timings()
586 if (adev->pio_mode < XFER_PIO_0 + pio) in piix_set_timings()
599 master_data &= 0xff0f; in piix_set_timings()
603 slave_data &= (ap->port_no ? 0x0f : 0xf0); in piix_set_timings()
605 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) in piix_set_timings()
606 << (ap->port_no ? 4 : 0); in piix_set_timings()
609 master_data &= 0xccf0; in piix_set_timings()
614 (timings[pio][0] << 12) | in piix_set_timings()
619 master_data |= 0x4000; in piix_set_timings()
624 /* Ensure the UDMA bit is off - it will be turned back on if in piix_set_timings()
627 if (ap->udma_mask) { in piix_set_timings()
628 pci_read_config_byte(dev, 0x48, &udma_enable); in piix_set_timings()
629 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); in piix_set_timings()
630 pci_write_config_byte(dev, 0x48, udma_enable); in piix_set_timings()
637 * piix_set_piomode - Initialize host controller PATA PIO timings
649 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0); in piix_set_piomode()
653 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
666 struct pci_dev *dev = to_pci_dev(ap->host->dev); in do_pata_set_dmamode()
668 u8 speed = adev->dma_mode; in do_pata_set_dmamode()
669 int devid = adev->devno + 2 * ap->port_no; in do_pata_set_dmamode()
670 u8 udma_enable = 0; in do_pata_set_dmamode()
673 unsigned int udma = speed - XFER_UDMA_0; in do_pata_set_dmamode()
680 pci_read_config_byte(dev, 0x48, &udma_enable); in do_pata_set_dmamode()
689 u_speed = min(2 - (udma & 1), udma); in do_pata_set_dmamode()
691 u_clock = 0x1000; /* 100Mhz */ in do_pata_set_dmamode()
695 u_clock = 0; /* 33Mhz */ in do_pata_set_dmamode()
700 pci_read_config_word(dev, 0x4A, &udma_timing); in do_pata_set_dmamode()
703 pci_write_config_word(dev, 0x4A, udma_timing); in do_pata_set_dmamode()
707 pci_read_config_word(dev, 0x54, &ideconf); in do_pata_set_dmamode()
708 ideconf &= ~(0x1001 << devid); in do_pata_set_dmamode()
712 pci_write_config_word(dev, 0x54, ideconf); in do_pata_set_dmamode()
715 pci_write_config_byte(dev, 0x48, udma_enable); in do_pata_set_dmamode()
720 unsigned int mwdma = speed - XFER_MW_DMA_0; in do_pata_set_dmamode()
724 int pio = needed_pio[mwdma] - XFER_PIO_0; in do_pata_set_dmamode()
732 * piix_set_dmamode - Initialize host controller PATA DMA timings
744 do_pata_set_dmamode(ap, adev, 0); in piix_set_dmamode()
748 * ich_set_dmamode - Initialize host controller PATA DMA timings
772 [SCR_STATUS] = 0,
779 struct ata_port *ap = link->ap; in piix_sidpr_sel()
780 struct piix_host_priv *hpriv = ap->host->private_data; in piix_sidpr_sel()
782 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], in piix_sidpr_sel()
783 hpriv->sidpr + PIIX_SIDPR_IDX); in piix_sidpr_sel()
789 struct piix_host_priv *hpriv = link->ap->host->private_data; in piix_sidpr_scr_read()
792 return -EINVAL; in piix_sidpr_scr_read()
795 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); in piix_sidpr_scr_read()
796 return 0; in piix_sidpr_scr_read()
802 struct piix_host_priv *hpriv = link->ap->host->private_data; in piix_sidpr_scr_write()
805 return -EINVAL; in piix_sidpr_scr_write()
808 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); in piix_sidpr_scr_write()
809 return 0; in piix_sidpr_scr_write()
822 if (unlikely(!ap->ioaddr.bmdma_addr)) in piix_irq_check()
825 host_stat = ap->ops->bmdma_status(ap); in piix_irq_check()
961 .ident = "VGN-BX297XP", in piix_broken_suspend()
964 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), in piix_broken_suspend()
989 return 0; in piix_broken_suspend()
1011 if (pdev->current_state == PCI_D0) in piix_pci_device_suspend()
1012 pdev->current_state = PCI_UNKNOWN; in piix_pci_device_suspend()
1015 spin_lock_irqsave(&host->lock, flags); in piix_pci_device_suspend()
1016 host->flags |= PIIX_HOST_BROKEN_SUSPEND; in piix_pci_device_suspend()
1017 spin_unlock_irqrestore(&host->lock, flags); in piix_pci_device_suspend()
1021 return 0; in piix_pci_device_suspend()
1030 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { in piix_pci_device_resume()
1031 spin_lock_irqsave(&host->lock, flags); in piix_pci_device_resume()
1032 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; in piix_pci_device_resume()
1033 spin_unlock_irqrestore(&host->lock, flags); in piix_pci_device_resume()
1044 dev_err(&pdev->dev, in piix_pci_device_resume()
1050 if (rc == 0) in piix_pci_device_resume()
1116 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1124 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1129 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1232 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1272 #define AHCI_GLOBAL_CTL 0x04
1278 int rc = 0; in piix_disable_ahci()
1286 return 0; in piix_disable_ahci()
1290 return -ENOMEM; in piix_disable_ahci()
1299 rc = -EIO; in piix_disable_ahci()
1307 * piix_check_450nx_errata - Check for problem 450NX setup
1318 int no_piix_dma = 0; in piix_check_450nx_errata()
1323 pci_read_config_word(pdev, 0x41, &cfg); in piix_check_450nx_errata()
1325 if (pdev->revision == 0x00) in piix_check_450nx_errata()
1328 else if (cfg & (1<<14) && pdev->revision < 5) in piix_check_450nx_errata()
1332 dev_warn(&ata_dev->dev, in piix_check_450nx_errata()
1334 no_piix_dma == 2 ? " - a BIOS update may resolve this" in piix_check_450nx_errata()
1343 struct pci_dev *pdev = to_pci_dev(host->dev); in piix_init_pcs()
1348 new_pcs = pcs | map_db->port_enable; in piix_init_pcs()
1361 int i, invalid_map = 0; in piix_init_sata_map()
1368 map = map_db->map[map_value & map_db->mask]; in piix_init_sata_map()
1370 for (i = 0; i < 4; i++) { in piix_init_sata_map()
1374 p += scnprintf(p, end - p, " XX"); in piix_init_sata_map()
1378 p += scnprintf(p, end - p, " --"); in piix_init_sata_map()
1385 p += scnprintf(p, end - p, " IDE IDE"); in piix_init_sata_map()
1389 p += scnprintf(p, end - p, " P%d", map[i]); in piix_init_sata_map()
1395 dev_info(&pdev->dev, "MAP [%s ]\n", buf); in piix_init_sata_map()
1398 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value); in piix_init_sata_map()
1405 struct pci_dev *pdev = to_pci_dev(host->dev); in piix_no_sidpr()
1408 * Samsung DB-P70 only has three ATA ports exposed and in piix_no_sidpr()
1425 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && in piix_no_sidpr()
1426 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && in piix_no_sidpr()
1427 pdev->subsystem_device == 0xb049) { in piix_no_sidpr()
1428 dev_warn(host->dev, in piix_no_sidpr()
1429 "Samsung DB-P70 detected, disabling SIDPR\n"); in piix_no_sidpr()
1438 struct pci_dev *pdev = to_pci_dev(host->dev); in piix_init_sidpr()
1439 struct piix_host_priv *hpriv = host->private_data; in piix_init_sidpr()
1440 struct ata_link *link0 = &host->ports[0]->link; in piix_init_sidpr()
1445 for (i = 0; i < 4; i++) in piix_init_sidpr()
1446 if (hpriv->map[i] == IDE) in piix_init_sidpr()
1447 return 0; in piix_init_sidpr()
1450 return 0; in piix_init_sidpr()
1452 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) in piix_init_sidpr()
1453 return 0; in piix_init_sidpr()
1455 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || in piix_init_sidpr()
1457 return 0; in piix_init_sidpr()
1460 return 0; in piix_init_sidpr()
1462 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; in piix_init_sidpr()
1471 * un-inhibit power save modes as BIOS might have inhibited in piix_init_sidpr()
1474 if ((scontrol & 0xf00) != 0x300) { in piix_init_sidpr()
1475 scontrol |= 0x300; in piix_init_sidpr()
1479 if ((scontrol & 0xf00) != 0x300) { in piix_init_sidpr()
1480 dev_info(host->dev, in piix_init_sidpr()
1482 return 0; in piix_init_sidpr()
1487 for (i = 0; i < 2; i++) { in piix_init_sidpr()
1488 struct ata_port *ap = host->ports[i]; in piix_init_sidpr()
1490 ap->ops = &piix_sidpr_sata_ops; in piix_init_sidpr()
1492 if (ap->flags & ATA_FLAG_SLAVE_POSS) { in piix_init_sidpr()
1499 return 0; in piix_init_sidpr()
1519 struct pci_dev *pdev = to_pci_dev(host->dev); in piix_iocfg_bit18_quirk()
1520 struct piix_host_priv *hpriv = host->private_data; in piix_iocfg_bit18_quirk()
1529 if (hpriv->saved_iocfg & (1 << 18)) { in piix_iocfg_bit18_quirk()
1530 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n"); in piix_iocfg_bit18_quirk()
1532 hpriv->saved_iocfg & ~(1 << 18)); in piix_iocfg_bit18_quirk()
1542 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), in piix_broken_system_poweroff()
1546 .driver_data = (void *)0x1FUL, in piix_broken_system_poweroff()
1551 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), in piix_broken_system_poweroff()
1555 .driver_data = (void *)0x1FUL, in piix_broken_system_poweroff()
1563 unsigned long slot = (unsigned long)dmi->driver_data; in piix_broken_system_poweroff()
1564 /* apply the quirk only to on-board controllers */ in piix_broken_system_poweroff()
1565 return slot == PCI_SLOT(pdev->devfn); in piix_broken_system_poweroff()
1572 module_param(prefer_ms_hyperv, int, 0);
1574 "Prefer Hyper-V paravirtualization drivers instead of ATA, "
1575 "0 - Use ATA drivers, "
1576 "1 (Default) - Use the paravirtualization drivers.");
1583 /* On Hyper-V hypervisors the disks are exposed on in piix_ignore_devices_quirk()
1584 * both the emulated SATA controller and on the in piix_ignore_devices_quirk()
1589 .ident = "Hyper-V Virtual Machine", in piix_ignore_devices_quirk()
1601 * identical to a Hyper-V guest. One difference is the in piix_ignore_devices_quirk()
1620 host->flags |= ATA_HOST_IGNORE_ATA; in piix_ignore_devices_quirk()
1621 dev_info(host->dev, "%s detected, ATA device ignore set\n", in piix_ignore_devices_quirk()
1622 ignore->ident); in piix_ignore_devices_quirk()
1628 * piix_init_one - Register PIIX ATA PCI device with kernel services
1639 * Zero on success, or -ERRNO value.
1644 struct device *dev = &pdev->dev; in piix_init_one()
1646 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; in piix_init_one()
1653 ata_print_version_once(&pdev->dev, DRV_VERSION); in piix_init_one()
1656 if (!in_module_init && ent->driver_data >= ich5_sata) in piix_init_one()
1657 return -ENODEV; in piix_init_one()
1660 piix_port_info[ent->driver_data].flags |= in piix_init_one()
1663 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " in piix_init_one()
1667 port_info[0] = piix_port_info[ent->driver_data]; in piix_init_one()
1668 port_info[1] = piix_port_info[ent->driver_data]; in piix_init_one()
1670 port_flags = port_info[0].flags; in piix_init_one()
1679 return -ENOMEM; in piix_init_one()
1686 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); in piix_init_one()
1692 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { in piix_init_one()
1698 /* SATA map init can change port_info, do it before prepping host */ in piix_init_one()
1700 hpriv->map = piix_init_sata_map(pdev, port_info, in piix_init_one()
1701 piix_map_db_table[ent->driver_data]); in piix_init_one()
1706 host->private_data = hpriv; in piix_init_one()
1710 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); in piix_init_one()
1714 if (host->ports[0]->ops == &piix_sidpr_sata_ops) in piix_init_one()
1725 * message-signalled interrupts currently). in piix_init_one()
1734 host->ports[0]->mwdma_mask = 0; in piix_init_one()
1735 host->ports[0]->udma_mask = 0; in piix_init_one()
1736 host->ports[1]->mwdma_mask = 0; in piix_init_one()
1737 host->ports[1]->udma_mask = 0; in piix_init_one()
1739 host->flags |= ATA_HOST_PARALLEL_SCAN; in piix_init_one()
1751 struct piix_host_priv *hpriv = host->private_data; in piix_remove_one()
1753 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); in piix_remove_one()
1777 in_module_init = 0; in piix_init()
1779 return 0; in piix_init()