Lines Matching +full:timestamp +full:- +full:names
1 /* SPDX-License-Identifier: MIT */
3 * Copyright (c) 2020-2024, Intel Corporation.
11 * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
32 * API header changed (field names, documentation, formatting) but API itself has not been changed
68 * Size of primary preemption buffer, assuming a 2-job submission queue.
74 * Size of secondary preemption buffer, assuming a 2-job submission queue.
79 /* Space reserved for future preemption-related fields. */
214 /* Clock frequencies: 0x20 - 0xFF */
219 /* Memory regions: 0x100 - 0x1FF */
239 /* IRQ re-direct numbers: 0x200 - 0x2FF */
242 /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
244 /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
246 /* VPU -> ARM IRQ line to use to request MMU update. */
248 /* ARM -> VPU IRQ line to use to notify of MMU update completion. */
250 /* ARM -> VPU IRQ line to use to request power level change. */
252 /* VPU -> ARM IRQ line to use to notify of power level change completion. */
254 /* VPU -> ARM IRQ line to use to notify of VPU idle state change */
256 /* VPU -> ARM IRQ line to use to request counter reset. */
258 /* ARM -> VPU IRQ line to use to notify of counter reset completion. */
260 /* VPU -> ARM IRQ line to use to notify of preemption completion. */
264 /* Silicon information: 0x300 - 0x3FF */
279 * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
313 * 0 - Default, DVFS mode selected by the firmware
314 * 1 - Max Performance
315 * 2 - On Demand
316 * 3 - Power Save
317 * 4 - On Demand Priority Aware
322 * On-demand: Default if 0.
323 * Bit 0-7 - uint8_t: Highest residency percent
324 * Bit 8-15 - uint8_t: High residency percent
325 * Bit 16-23 - uint8_t: Low residency percent
326 * Bit 24-31 - uint8_t: Lowest residency percent
327 * Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
328 * Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
329 * Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
330 * Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
331 * Bit 48-55 - uint8_t: Period (ms) for residency decisions
332 * Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
358 * HW timestamp register, in ticks. Written by the firmware during boot.
363 /* Warm boot information: 0x400 - 0x43F */
368 /* Power States transitions timestamps: 0x440 - 0x46F*/
370 /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
372 /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
374 /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
376 /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
378 /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
380 /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
395 /* Unused/reserved: 0x488 - 0xFFF */
433 /* legacy field - do not use */
447 * 0 - null terminated string
448 * 1 - size + null terminated string
449 * 2 - MIPI-SysT encoding
454 * 0 - messages are place 1 after another
455 * n - every message starts and multiple on offset