Lines Matching full:val
73 u32 val = 0; in host_ss_rst_clr() local
75 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in host_ss_rst_clr()
76 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in host_ss_rst_clr()
77 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in host_ss_rst_clr()
79 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in host_ss_rst_clr()
84 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_37xx() local
86 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_37xx()
94 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_40xx() local
96 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qreqn_check_40xx()
112 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_37xx() local
114 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qacceptn_check_37xx()
122 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); in host_ss_noc_qacceptn_check_40xx() local
124 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qacceptn_check_40xx()
140 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_37xx() local
142 if (!REG_TEST_FLD_NUM(VPU_37XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qdeny_check_37xx()
150 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_40xx() local
152 if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) in host_ss_noc_qdeny_check_40xx()
168 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_37xx() local
170 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in top_noc_qrenqn_check_37xx()
171 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qrenqn_check_37xx()
179 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_40xx() local
181 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in top_noc_qrenqn_check_40xx()
182 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qrenqn_check_40xx()
230 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN); in idle_gen_drive_37xx() local
233 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
235 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
237 REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val); in idle_gen_drive_37xx()
242 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); in idle_gen_drive_40xx() local
245 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
247 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
249 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); in idle_gen_drive_40xx()
271 u32 val; in pwr_island_delay_set_50xx() local
273 val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY); in pwr_island_delay_set_50xx()
274 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val); in pwr_island_delay_set_50xx()
275 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST1_DLY, post1, val); in pwr_island_delay_set_50xx()
276 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST2_DLY, post2, val); in pwr_island_delay_set_50xx()
277 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val); in pwr_island_delay_set_50xx()
279 val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY); in pwr_island_delay_set_50xx()
280 val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, val); in pwr_island_delay_set_50xx()
281 REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val); in pwr_island_delay_set_50xx()
286 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); in pwr_island_trickle_drive_37xx() local
289 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in pwr_island_trickle_drive_37xx()
291 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in pwr_island_trickle_drive_37xx()
293 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in pwr_island_trickle_drive_37xx()
298 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); in pwr_island_trickle_drive_40xx() local
301 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); in pwr_island_trickle_drive_40xx()
303 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); in pwr_island_trickle_drive_40xx()
305 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in pwr_island_trickle_drive_40xx()
310 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); in pwr_island_drive_37xx() local
313 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); in pwr_island_drive_37xx()
315 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); in pwr_island_drive_37xx()
317 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in pwr_island_drive_37xx()
322 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); in pwr_island_drive_40xx() local
325 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); in pwr_island_drive_40xx()
327 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); in pwr_island_drive_40xx()
329 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); in pwr_island_drive_40xx()
360 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); in pwr_island_isolation_drive_37xx() local
363 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in pwr_island_isolation_drive_37xx()
365 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in pwr_island_isolation_drive_37xx()
367 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); in pwr_island_isolation_drive_37xx()
372 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); in pwr_island_isolation_drive_40xx() local
375 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); in pwr_island_isolation_drive_40xx()
377 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); in pwr_island_isolation_drive_40xx()
379 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); in pwr_island_isolation_drive_40xx()
397 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); in host_ss_clk_drive_37xx() local
400 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in host_ss_clk_drive_37xx()
401 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in host_ss_clk_drive_37xx()
402 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in host_ss_clk_drive_37xx()
404 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in host_ss_clk_drive_37xx()
405 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in host_ss_clk_drive_37xx()
406 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in host_ss_clk_drive_37xx()
409 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); in host_ss_clk_drive_37xx()
414 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); in host_ss_clk_drive_40xx() local
417 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in host_ss_clk_drive_40xx()
418 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in host_ss_clk_drive_40xx()
419 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in host_ss_clk_drive_40xx()
421 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in host_ss_clk_drive_40xx()
422 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in host_ss_clk_drive_40xx()
423 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in host_ss_clk_drive_40xx()
426 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val); in host_ss_clk_drive_40xx()
444 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); in host_ss_rst_drive_37xx() local
447 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); in host_ss_rst_drive_37xx()
448 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); in host_ss_rst_drive_37xx()
449 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); in host_ss_rst_drive_37xx()
451 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, TOP_NOC, val); in host_ss_rst_drive_37xx()
452 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, DSS_MAS, val); in host_ss_rst_drive_37xx()
453 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_RST_SET, MSS_MAS, val); in host_ss_rst_drive_37xx()
456 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_SET, val); in host_ss_rst_drive_37xx()
461 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); in host_ss_rst_drive_40xx() local
464 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in host_ss_rst_drive_40xx()
465 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in host_ss_rst_drive_40xx()
466 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in host_ss_rst_drive_40xx()
468 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in host_ss_rst_drive_40xx()
469 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in host_ss_rst_drive_40xx()
470 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in host_ss_rst_drive_40xx()
473 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val); in host_ss_rst_drive_40xx()
491 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_top_socmmio_drive_37xx() local
494 val = REG_SET_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_37xx()
496 val = REG_CLR_FLD(VPU_37XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_37xx()
497 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); in host_ss_noc_qreqn_top_socmmio_drive_37xx()
502 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_top_socmmio_drive_40xx() local
505 val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_40xx()
507 val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in host_ss_noc_qreqn_top_socmmio_drive_40xx()
508 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); in host_ss_noc_qreqn_top_socmmio_drive_40xx()
540 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in top_noc_qreqn_drive_40xx() local
543 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
544 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_40xx()
546 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
547 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_40xx()
550 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); in top_noc_qreqn_drive_40xx()
555 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); in top_noc_qreqn_drive_37xx() local
558 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_37xx()
559 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_37xx()
561 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_37xx()
562 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in top_noc_qreqn_drive_37xx()
565 REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val); in top_noc_qreqn_drive_37xx()
583 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); in top_noc_qacceptn_check_37xx() local
585 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in top_noc_qacceptn_check_37xx()
586 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qacceptn_check_37xx()
594 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); in top_noc_qacceptn_check_40xx() local
596 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in top_noc_qacceptn_check_40xx()
597 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qacceptn_check_40xx()
613 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); in top_noc_qdeny_check_37xx() local
615 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in top_noc_qdeny_check_37xx()
616 !REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qdeny_check_37xx()
624 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); in top_noc_qdeny_check_40xx() local
626 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in top_noc_qdeny_check_40xx()
627 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) in top_noc_qdeny_check_40xx()
667 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE); in dpu_active_drive_37xx() local
670 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); in dpu_active_drive_37xx()
672 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); in dpu_active_drive_37xx()
674 REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val); in dpu_active_drive_37xx()
741 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); in ivpu_hw_ip_snoop_disable_37xx() local
743 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val); in ivpu_hw_ip_snoop_disable_37xx()
744 val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_37xx()
747 val = REG_CLR_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_37xx()
749 val = REG_SET_FLD(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_37xx()
751 REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val); in ivpu_hw_ip_snoop_disable_37xx()
756 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES); in ivpu_hw_ip_snoop_disable_40xx() local
758 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val); in ivpu_hw_ip_snoop_disable_40xx()
759 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_40xx()
762 val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_40xx()
764 val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); in ivpu_hw_ip_snoop_disable_40xx()
766 REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val); in ivpu_hw_ip_snoop_disable_40xx()
779 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); in ivpu_hw_ip_tbu_mmu_enable_37xx() local
781 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
782 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
783 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
784 val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
786 REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_37xx()
791 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); in ivpu_hw_ip_tbu_mmu_enable_40xx() local
793 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
794 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
795 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
796 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
797 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
798 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
800 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
813 u32 val; in soc_cpu_boot_37xx() local
815 val = REGV_RD32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC); in soc_cpu_boot_37xx()
816 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val); in soc_cpu_boot_37xx()
818 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val); in soc_cpu_boot_37xx()
819 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in soc_cpu_boot_37xx()
821 val = REG_SET_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); in soc_cpu_boot_37xx()
822 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in soc_cpu_boot_37xx()
824 val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); in soc_cpu_boot_37xx()
825 REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in soc_cpu_boot_37xx()
827 val = vdev->fw->entry_point >> 9; in soc_cpu_boot_37xx()
828 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); in soc_cpu_boot_37xx()
830 val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val); in soc_cpu_boot_37xx()
831 REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); in soc_cpu_boot_37xx()
841 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN); in cpu_noc_qacceptn_check_40xx() local
843 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN, TOP_MMIO, exp_val, val)) in cpu_noc_qacceptn_check_40xx()
851 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QDENY); in cpu_noc_qdeny_check_40xx() local
853 if (!REG_TEST_FLD_NUM(VPU_40XX_CPU_SS_CPR_NOC_QDENY, TOP_MMIO, exp_val, val)) in cpu_noc_qdeny_check_40xx()
861 u32 val = REGV_RD32(VPU_40XX_CPU_SS_CPR_NOC_QREQN); in cpu_noc_top_mmio_drive_40xx() local
864 val = REG_SET_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); in cpu_noc_top_mmio_drive_40xx()
866 val = REG_CLR_FLD(VPU_40XX_CPU_SS_CPR_NOC_QREQN, TOP_MMIO, val); in cpu_noc_top_mmio_drive_40xx()
867 REGV_WR32(VPU_40XX_CPU_SS_CPR_NOC_QREQN, val); in cpu_noc_top_mmio_drive_40xx()
897 u32 val; in soc_cpu_boot_40xx() local
910 val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO); in soc_cpu_boot_40xx()
911 val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val); in soc_cpu_boot_40xx()
912 REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val); in soc_cpu_boot_40xx()
930 u32 val; in wdt_disable_37xx() local
941 val = REGV_RD32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG); in wdt_disable_37xx()
942 val = REG_CLR_FLD(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); in wdt_disable_37xx()
943 REGV_WR32(VPU_37XX_CPU_SS_TIM_GEN_CONFIG, val); in wdt_disable_37xx()
948 u32 val; in wdt_disable_40xx() local
956 val = REGV_RD32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG); in wdt_disable_40xx()
957 val = REG_CLR_FLD(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); in wdt_disable_40xx()
958 REGV_WR32(VPU_40XX_CPU_SS_TIM_GEN_CONFIG, val); in wdt_disable_40xx()
1153 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET); in db_set_37xx() local
1155 REGV_WR32I(VPU_37XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); in db_set_37xx()
1161 u32 val = REG_FLD(VPU_40XX_CPU_SS_DOORBELL_0, SET); in db_set_40xx() local
1163 REGV_WR32I(VPU_40XX_CPU_SS_DOORBELL_0, reg_stride, db_id, val); in db_set_40xx()