63 static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio);
65 int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev)  in ivpu_hw_btrs_irqs_clear_with_0_mtl()  argument
77 static void freq_ratios_init_mtl(struct ivpu_device *vdev)  in freq_ratios_init_mtl()  argument
79 	struct ivpu_hw_info *hw = vdev->hw;  in freq_ratios_init_mtl()
90 static void freq_ratios_init_lnl(struct ivpu_device *vdev)  in freq_ratios_init_lnl()  argument
92 	struct ivpu_hw_info *hw = vdev->hw;  in freq_ratios_init_lnl()
103 void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev)  in ivpu_hw_btrs_freq_ratios_init()  argument
105 	struct ivpu_hw_info *hw = vdev->hw;  in ivpu_hw_btrs_freq_ratios_init()
107 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_freq_ratios_init()
108 		freq_ratios_init_mtl(vdev);  in ivpu_hw_btrs_freq_ratios_init()
110 		freq_ratios_init_lnl(vdev);  in ivpu_hw_btrs_freq_ratios_init()
132 static int read_tile_config_fuse(struct ivpu_device *vdev, u32 *tile_fuse_config)  in read_tile_config_fuse()  argument
139 		ivpu_err(vdev, "Fuse: invalid (0x%x)\n", fuse);  in read_tile_config_fuse()
145 		ivpu_warn(vdev, "More than 1 tile disabled, tile fuse config mask: 0x%x\n", config);  in read_tile_config_fuse()
147 	ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config);  in read_tile_config_fuse()
153 static int info_init_mtl(struct ivpu_device *vdev)  in info_init_mtl()  argument
155 	struct ivpu_hw_info *hw = vdev->hw;  in info_init_mtl()
164 static int info_init_lnl(struct ivpu_device *vdev)  in info_init_lnl()  argument
166 	struct ivpu_hw_info *hw = vdev->hw;  in info_init_lnl()
170 	ret = read_tile_config_fuse(vdev, &tile_fuse_config);  in info_init_lnl()
180 int ivpu_hw_btrs_info_init(struct ivpu_device *vdev)  in ivpu_hw_btrs_info_init()  argument
182 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_info_init()
183 		return info_init_mtl(vdev);  in ivpu_hw_btrs_info_init()
185 		return info_init_lnl(vdev);  in ivpu_hw_btrs_info_init()
188 static int wp_request_sync(struct ivpu_device *vdev)  in wp_request_sync()  argument
190 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in wp_request_sync()
196 static int wait_for_status_ready(struct ivpu_device *vdev, bool enable)  in wait_for_status_ready()  argument
203 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in wait_for_status_ready()
218 static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_mtl()  argument
241 static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_lnl()  argument
265 static void wp_request(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request()  argument
267 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in wp_request()
268 		wp_request_mtl(vdev, wp);  in wp_request()
270 		wp_request_lnl(vdev, wp);  in wp_request()
273 static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_send()  argument
277 	ret = wp_request_sync(vdev);  in wp_request_send()
279 		ivpu_err(vdev, "Failed to sync before workpoint request: %d\n", ret);  in wp_request_send()
283 	wp_request(vdev, wp);  in wp_request_send()
285 	ret = wp_request_sync(vdev);  in wp_request_send()
287 		ivpu_err(vdev, "Failed to sync after workpoint request: %d\n", ret);  in wp_request_send()
292 static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable)  in prepare_wp_request()  argument
294 	struct ivpu_hw_info *hw = vdev->hw;  in prepare_wp_request()
299 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {  in prepare_wp_request()
312 static int wait_for_pll_lock(struct ivpu_device *vdev, bool enable)  in wait_for_pll_lock()  argument
316 	if (ivpu_hw_btrs_gen(vdev) != IVPU_HW_BTRS_MTL)  in wait_for_pll_lock()
325 int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable)  in ivpu_hw_btrs_wp_drive()  argument
331 		ivpu_dbg(vdev, PM, "Skipping workpoint request\n");  in ivpu_hw_btrs_wp_drive()
335 	prepare_wp_request(vdev, &wp, enable);  in ivpu_hw_btrs_wp_drive()
337 	ivpu_dbg(vdev, PM, "PLL workpoint request: %lu MHz, config: 0x%x, epp: 0x%x, cdyn: 0x%x\n",  in ivpu_hw_btrs_wp_drive()
338 		 pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn);  in ivpu_hw_btrs_wp_drive()
340 	ret = wp_request_send(vdev, &wp);  in ivpu_hw_btrs_wp_drive()
342 		ivpu_err(vdev, "Failed to send workpoint request: %d\n", ret);  in ivpu_hw_btrs_wp_drive()
346 	ret = wait_for_pll_lock(vdev, enable);  in ivpu_hw_btrs_wp_drive()
348 		ivpu_err(vdev, "Timed out waiting for PLL lock\n");  in ivpu_hw_btrs_wp_drive()
352 	ret = wait_for_status_ready(vdev, enable);  in ivpu_hw_btrs_wp_drive()
354 		ivpu_err(vdev, "Timed out waiting for NPU ready status\n");  in ivpu_hw_btrs_wp_drive()
361 static int d0i3_drive_mtl(struct ivpu_device *vdev, bool enable)  in d0i3_drive_mtl()  argument
368 		ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);  in d0i3_drive_mtl()
381 		ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);  in d0i3_drive_mtl()
386 static int d0i3_drive_lnl(struct ivpu_device *vdev, bool enable)  in d0i3_drive_lnl()  argument
393 		ivpu_err(vdev, "Failed to sync before D0i3 transition: %d\n", ret);  in d0i3_drive_lnl()
406 		ivpu_err(vdev, "Failed to sync after D0i3 transition: %d\n", ret);  in d0i3_drive_lnl()
413 static int d0i3_drive(struct ivpu_device *vdev, bool enable)  in d0i3_drive()  argument
415 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in d0i3_drive()
416 		return d0i3_drive_mtl(vdev, enable);  in d0i3_drive()
418 		return d0i3_drive_lnl(vdev, enable);  in d0i3_drive()
421 int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev)  in ivpu_hw_btrs_d0i3_enable()  argument
428 	ret = d0i3_drive(vdev, true);  in ivpu_hw_btrs_d0i3_enable()
430 		ivpu_err(vdev, "Failed to enable D0i3: %d\n", ret);  in ivpu_hw_btrs_d0i3_enable()
437 int ivpu_hw_btrs_d0i3_disable(struct ivpu_device *vdev)  in ivpu_hw_btrs_d0i3_disable()  argument
444 	ret = d0i3_drive(vdev, false);  in ivpu_hw_btrs_d0i3_disable()
446 		ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);  in ivpu_hw_btrs_d0i3_disable()
451 int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev)  in ivpu_hw_btrs_wait_for_clock_res_own_ack()  argument
453 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_wait_for_clock_res_own_ack()
459 void ivpu_hw_btrs_set_port_arbitration_weights_lnl(struct ivpu_device *vdev)  in ivpu_hw_btrs_set_port_arbitration_weights_lnl()  argument
465 static int ip_reset_mtl(struct ivpu_device *vdev)  in ip_reset_mtl()  argument
472 		ivpu_err(vdev, "Timed out waiting for TRIGGER bit\n");  in ip_reset_mtl()
482 		ivpu_err(vdev, "Timed out waiting for RESET completion\n");  in ip_reset_mtl()
487 static int ip_reset_lnl(struct ivpu_device *vdev)  in ip_reset_lnl()  argument
492 	ivpu_hw_btrs_clock_relinquish_disable_lnl(vdev);  in ip_reset_lnl()
496 		ivpu_err(vdev, "Wait for *_TRIGGER timed out\n");  in ip_reset_lnl()
506 		ivpu_err(vdev, "Timed out waiting for RESET completion\n");  in ip_reset_lnl()
511 int ivpu_hw_btrs_ip_reset(struct ivpu_device *vdev)  in ivpu_hw_btrs_ip_reset()  argument
516 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_ip_reset()
517 		return ip_reset_mtl(vdev);  in ivpu_hw_btrs_ip_reset()
519 		return ip_reset_lnl(vdev);  in ivpu_hw_btrs_ip_reset()
522 void ivpu_hw_btrs_profiling_freq_reg_set_lnl(struct ivpu_device *vdev)  in ivpu_hw_btrs_profiling_freq_reg_set_lnl()  argument
526 	if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)  in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
534 void ivpu_hw_btrs_ats_print_lnl(struct ivpu_device *vdev)  in ivpu_hw_btrs_ats_print_lnl()  argument
536 	ivpu_dbg(vdev, MISC, "Buttress ATS: %s\n",  in ivpu_hw_btrs_ats_print_lnl()
540 void ivpu_hw_btrs_clock_relinquish_disable_lnl(struct ivpu_device *vdev)  in ivpu_hw_btrs_clock_relinquish_disable_lnl()  argument
548 bool ivpu_hw_btrs_is_idle(struct ivpu_device *vdev)  in ivpu_hw_btrs_is_idle()  argument
555 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {  in ivpu_hw_btrs_is_idle()
568 int ivpu_hw_btrs_wait_for_idle(struct ivpu_device *vdev)  in ivpu_hw_btrs_wait_for_idle()  argument
570 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_wait_for_idle()
576 static u32 pll_config_get_mtl(struct ivpu_device *vdev)  in pll_config_get_mtl()  argument
581 static u32 pll_config_get_lnl(struct ivpu_device *vdev)  in pll_config_get_lnl()  argument
596 static u32 pll_ratio_to_dpu_freq(struct ivpu_device *vdev, u32 ratio)  in pll_ratio_to_dpu_freq()  argument
598 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in pll_ratio_to_dpu_freq()
604 u32 ivpu_hw_btrs_dpu_max_freq_get(struct ivpu_device *vdev)  in ivpu_hw_btrs_dpu_max_freq_get()  argument
606 	return pll_ratio_to_dpu_freq(vdev, vdev->hw->pll.max_ratio);  in ivpu_hw_btrs_dpu_max_freq_get()
610 bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq)  in ivpu_hw_btrs_irq_handler_mtl()  argument
619 		u32 pll = pll_config_get_mtl(vdev);  in ivpu_hw_btrs_irq_handler_mtl()
621 		ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",  in ivpu_hw_btrs_irq_handler_mtl()
626 		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));  in ivpu_hw_btrs_irq_handler_mtl()
634 		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",  in ivpu_hw_btrs_irq_handler_mtl()
653 		ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");  in ivpu_hw_btrs_irq_handler_mtl()
659 bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq)  in ivpu_hw_btrs_irq_handler_lnl()  argument
668 		ivpu_dbg(vdev, IRQ, "Survivability IRQ\n");  in ivpu_hw_btrs_irq_handler_lnl()
669 		if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_DCT))  in ivpu_hw_btrs_irq_handler_lnl()
670 			ivpu_err_ratelimited(vdev, "IRQ FIFO full\n");  in ivpu_hw_btrs_irq_handler_lnl()
674 		u32 pll = pll_config_get_lnl(vdev);  in ivpu_hw_btrs_irq_handler_lnl()
676 		ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",  in ivpu_hw_btrs_irq_handler_lnl()
681 		ivpu_err(vdev, "ATS_ERR LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",  in ivpu_hw_btrs_irq_handler_lnl()
689 		ivpu_err(vdev, "CFI0_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));  in ivpu_hw_btrs_irq_handler_lnl()
695 		ivpu_err(vdev, "CFI1_ERR 0x%08x", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));  in ivpu_hw_btrs_irq_handler_lnl()
701 		ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x",  in ivpu_hw_btrs_irq_handler_lnl()
709 		ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x",  in ivpu_hw_btrs_irq_handler_lnl()
720 		ivpu_pm_trigger_recovery(vdev, "Buttress IRQ");  in ivpu_hw_btrs_irq_handler_lnl()
725 int ivpu_hw_btrs_dct_get_request(struct ivpu_device *vdev, bool *enable)  in ivpu_hw_btrs_dct_get_request()  argument
732 		ivpu_err_ratelimited(vdev, "Unsupported PCODE command: 0x%x\n", cmd);  in ivpu_hw_btrs_dct_get_request()
744 		ivpu_err_ratelimited(vdev, "Invalid PARAM1 value: %u\n", param1);  in ivpu_hw_btrs_dct_get_request()
749 void ivpu_hw_btrs_dct_set_status(struct ivpu_device *vdev, bool enable, u32 active_percent)  in ivpu_hw_btrs_dct_set_status()  argument
761 u32 ivpu_hw_btrs_telemetry_offset_get(struct ivpu_device *vdev)  in ivpu_hw_btrs_telemetry_offset_get()  argument
763 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_telemetry_offset_get()
769 u32 ivpu_hw_btrs_telemetry_size_get(struct ivpu_device *vdev)  in ivpu_hw_btrs_telemetry_size_get()  argument
771 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_telemetry_size_get()
777 u32 ivpu_hw_btrs_telemetry_enable_get(struct ivpu_device *vdev)  in ivpu_hw_btrs_telemetry_enable_get()  argument
779 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_telemetry_enable_get()
785 void ivpu_hw_btrs_global_int_disable(struct ivpu_device *vdev)  in ivpu_hw_btrs_global_int_disable()  argument
787 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_global_int_disable()
793 void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev)  in ivpu_hw_btrs_global_int_enable()  argument
795 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_global_int_enable()
801 void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev)  in ivpu_hw_btrs_irq_enable()  argument
803 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {  in ivpu_hw_btrs_irq_enable()
812 void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev)  in ivpu_hw_btrs_irq_disable()  argument
814 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) {  in ivpu_hw_btrs_irq_disable()
823 static void diagnose_failure_mtl(struct ivpu_device *vdev)  in diagnose_failure_mtl()  argument
828 		ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0));  in diagnose_failure_mtl()
833 		ivpu_err(vdev, "UFI_ERR irq (0x%08x) opcode: 0x%02lx axi_id: 0x%02lx cq_id: 0x%03lx",  in diagnose_failure_mtl()
840 static void diagnose_failure_lnl(struct ivpu_device *vdev)  in diagnose_failure_lnl()  argument
845 		ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n",  in diagnose_failure_lnl()
851 		ivpu_err(vdev, "CFI0_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI0_ERR_LOG));  in diagnose_failure_lnl()
854 		ivpu_err(vdev, "CFI1_ERR_LOG 0x%08x\n", REGB_RD32(VPU_HW_BTRS_LNL_CFI1_ERR_LOG));  in diagnose_failure_lnl()
857 		ivpu_err(vdev, "IMR_ERR_CFI0 LOW: 0x%08x HIGH: 0x%08x\n",  in diagnose_failure_lnl()
862 		ivpu_err(vdev, "IMR_ERR_CFI1 LOW: 0x%08x HIGH: 0x%08x\n",  in diagnose_failure_lnl()
867 		ivpu_err(vdev, "Survivability IRQ\n");  in diagnose_failure_lnl()
870 void ivpu_hw_btrs_diagnose_failure(struct ivpu_device *vdev)  in ivpu_hw_btrs_diagnose_failure()  argument
872 	if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL)  in ivpu_hw_btrs_diagnose_failure()
873 		return diagnose_failure_mtl(vdev);  in ivpu_hw_btrs_diagnose_failure()
875 		return diagnose_failure_lnl(vdev);  in ivpu_hw_btrs_diagnose_failure()