1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2020-2025 Intel Corporation
29 #define BTRS_IRQ_DISABLE_MASK ((u32)-1)
31 #define BTRS_LNL_ALL_IRQ_MASK ((u32)-1)
79 	struct ivpu_hw_info *hw = vdev->hw;  in freq_ratios_init_mtl()
83 	hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, MIN_RATIO, fmin_fuse);  in freq_ratios_init_mtl()
84 	hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMIN_FUSE, PN_RATIO, fmin_fuse);  in freq_ratios_init_mtl()
87 	hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_MTL_FMAX_FUSE, MAX_RATIO, fmax_fuse);  in freq_ratios_init_mtl()
92 	struct ivpu_hw_info *hw = vdev->hw;  in freq_ratios_init_lnl()
96 	hw->pll.min_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, MIN_RATIO, fmin_fuse);  in freq_ratios_init_lnl()
97 	hw->pll.pn_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMIN_FUSE, PN_RATIO, fmin_fuse);  in freq_ratios_init_lnl()
100 	hw->pll.max_ratio = REG_GET_FLD(VPU_HW_BTRS_LNL_FMAX_FUSE, MAX_RATIO, fmax_fuse);  in freq_ratios_init_lnl()
105 	struct ivpu_hw_info *hw = vdev->hw;  in ivpu_hw_btrs_freq_ratios_init()
112 	hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, hw->pll.min_ratio, hw->pll.max_ratio);  in ivpu_hw_btrs_freq_ratios_init()
113 	hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, hw->pll.max_ratio);  in ivpu_hw_btrs_freq_ratios_init()
114 	hw->pll.pn_ratio = clamp_t(u8, hw->pll.pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);  in ivpu_hw_btrs_freq_ratios_init()
119 	/* Allowed values: 0 or one bit from range 0-5 (6 tiles) */  in tile_disable_check()
123 	if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1))  in tile_disable_check()
126 	if ((config & (config - 1)) == 0)  in tile_disable_check()
140 		return -EIO;  in read_tile_config_fuse()
147 	ivpu_dbg(vdev, MISC, "Tile disable config mask: 0x%x\n", config);  in read_tile_config_fuse()
155 	struct ivpu_hw_info *hw = vdev->hw;  in info_init_mtl()
157 	hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH;  in info_init_mtl()
158 	hw->sku = BTRS_MTL_TILE_SKU_BOTH;  in info_init_mtl()
159 	hw->config = WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3);  in info_init_mtl()
166 	struct ivpu_hw_info *hw = vdev->hw;  in info_init_lnl()
174 	hw->tile_fuse = tile_fuse_config;  in info_init_lnl()
175 	hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT;  in info_init_lnl()
218 static void wp_request_mtl(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_mtl()  argument
223 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);  in wp_request_mtl()
224 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);  in wp_request_mtl()
228 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);  in wp_request_mtl()
233 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);  in wp_request_mtl()
241 static void wp_request_lnl(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_lnl()  argument
246 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MIN_RATIO, wp->min, val);  in wp_request_lnl()
247 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD0, MAX_RATIO, wp->max, val);  in wp_request_lnl()
251 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, TARGET_RATIO, wp->target, val);  in wp_request_lnl()
252 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD1, EPP, wp->epp, val);  in wp_request_lnl()
256 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CONFIG, wp->cfg, val);  in wp_request_lnl()
257 	val = REG_SET_FLD_NUM(VPU_HW_BTRS_LNL_WP_REQ_PAYLOAD2, CDYN, wp->cdyn, val);  in wp_request_lnl()
265 static void wp_request(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request()  argument
268 		wp_request_mtl(vdev, wp);  in wp_request()
270 		wp_request_lnl(vdev, wp);  in wp_request()
273 static int wp_request_send(struct ivpu_device *vdev, struct wp_request *wp)  in wp_request_send()  argument
283 	wp_request(vdev, wp);  in wp_request_send()
292 static void prepare_wp_request(struct ivpu_device *vdev, struct wp_request *wp, bool enable)  in prepare_wp_request()  argument
294 	struct ivpu_hw_info *hw = vdev->hw;  in prepare_wp_request()
296 	wp->min = hw->pll.min_ratio;  in prepare_wp_request()
297 	wp->max = hw->pll.max_ratio;  in prepare_wp_request()
300 		wp->target = enable ? hw->pll.pn_ratio : 0;  in prepare_wp_request()
301 		wp->cfg = enable ? hw->config : 0;  in prepare_wp_request()
302 		wp->cdyn = 0;  in prepare_wp_request()
303 		wp->epp = 0;  in prepare_wp_request()
305 		wp->target = hw->pll.pn_ratio;  in prepare_wp_request()
306 		wp->cfg = enable ? PLL_CONFIG_DEFAULT : 0;  in prepare_wp_request()
307 		wp->cdyn = enable ? PLL_CDYN_DEFAULT : 0;  in prepare_wp_request()
308 		wp->epp = enable ? PLL_EPP_DEFAULT : 0;  in prepare_wp_request()
327 	struct wp_request wp;  in ivpu_hw_btrs_wp_drive()  local
335 	prepare_wp_request(vdev, &wp, enable);  in ivpu_hw_btrs_wp_drive()
338 		 pll_ratio_to_dpu_freq(vdev, wp.target) / HZ_PER_MHZ, wp.cfg, wp.epp, wp.cdyn);  in ivpu_hw_btrs_wp_drive()
340 	ret = wp_request_send(vdev, &wp);  in ivpu_hw_btrs_wp_drive()
446 		ivpu_err(vdev, "Failed to disable D0i3: %d\n", ret);  in ivpu_hw_btrs_d0i3_disable()
526 	if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT)  in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
537 		 REGB_RD32(VPU_HW_BTRS_LNL_HM_ATS) ? "Enable" : "Disable");  in ivpu_hw_btrs_ats_print_lnl()
606 	return pll_ratio_to_dpu_freq(vdev, vdev->hw->pll.max_ratio);  in ivpu_hw_btrs_dpu_max_freq_get()
621 		ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",  in ivpu_hw_btrs_irq_handler_mtl()
669 		if (!kfifo_put(&vdev->hw->irq.fifo, IVPU_HW_IRQ_SRC_DCT))  in ivpu_hw_btrs_irq_handler_lnl()
676 		ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq, wp %08x, %lu MHz",  in ivpu_hw_btrs_irq_handler_lnl()
733 		return -EBADR;  in ivpu_hw_btrs_dct_get_request()
745 		return -EINVAL;  in ivpu_hw_btrs_dct_get_request()