Lines Matching +full:4 +full:mb
13 #define DRAM_BAR_ID 4
16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
81 #define NUM_OF_DCORES 4
82 #define NUM_OF_SFT 4
86 #define NUM_OF_PQ_PER_QMAN 4
90 #define NUM_OF_HIF_PER_DCORE 4
99 #define NUM_OF_HMMU_PER_DCORE 4
107 #define NUM_OF_ARC_FARMS_ARC 4
108 #define NUM_OF_XBAR 4