Lines Matching +full:0 +full:- +full:1152

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
16 #define MPNPU_PUB_SEC_INTR             0x3010060
17 #define MPNPU_PUB_PWRMGMT_INTR         0x3010064
18 #define MPNPU_PUB_SCRATCH0             0x301006C
19 #define MPNPU_PUB_SCRATCH1             0x3010070
20 #define MPNPU_PUB_SCRATCH2             0x3010074
21 #define MPNPU_PUB_SCRATCH3             0x3010078
22 #define MPNPU_PUB_SCRATCH4             0x301007C
23 #define MPNPU_PUB_SCRATCH5             0x3010080
24 #define MPNPU_PUB_SCRATCH6             0x3010084
25 #define MPNPU_PUB_SCRATCH7             0x3010088
26 #define MPNPU_PUB_SCRATCH8             0x301008C
27 #define MPNPU_PUB_SCRATCH9             0x3010090
28 #define MPNPU_PUB_SCRATCH10            0x3010094
29 #define MPNPU_PUB_SCRATCH11            0x3010098
30 #define MPNPU_PUB_SCRATCH12            0x301009C
31 #define MPNPU_PUB_SCRATCH13            0x30100A0
32 #define MPNPU_PUB_SCRATCH14            0x30100A4
33 #define MPNPU_PUB_SCRATCH15            0x30100A8
34 #define MP0_C2PMSG_73                  0x3810A24
35 #define MP0_C2PMSG_123                 0x3810AEC
37 #define MP1_C2PMSG_0                   0x3B10900
38 #define MP1_C2PMSG_60                  0x3B109F0
39 #define MP1_C2PMSG_61                  0x3B109F4
41 #define MPNPU_SRAM_X2I_MAILBOX_0       0x3600000
42 #define MPNPU_SRAM_X2I_MAILBOX_15      0x361E000
43 #define MPNPU_SRAM_X2I_MAILBOX_31      0x363E000
44 #define MPNPU_SRAM_I2X_MAILBOX_31      0x363F000
46 #define MMNPU_APERTURE0_BASE           0x3000000
47 #define MMNPU_APERTURE1_BASE           0x3600000
48 #define MMNPU_APERTURE3_BASE           0x3810000
49 #define MMNPU_APERTURE4_BASE           0x3B10000
52 #define NPU4_REG_BAR_INDEX	0
53 #define NPU4_MBOX_BAR_INDEX	0
70 	{ 0 },
76 	{792, 1152},
80 	{1152, 1584},
82 	{ 0 }
87 	.protocol_major = 0x6,
93 	.mbox_size      = 0, /* Use BAR size */
126 	.first_col         = 0,
130 	.vbnv              = "RyzenAI-npu4",