25 static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd,  in aie2_smu_exec()  argument
31 	writel(0, SMU_REG(ndev, SMU_RESP_REG));  in aie2_smu_exec()
32 	writel(reg_arg, SMU_REG(ndev, SMU_ARG_REG));  in aie2_smu_exec()
33 	writel(reg_cmd, SMU_REG(ndev, SMU_CMD_REG));  in aie2_smu_exec()
36 	writel(0, SMU_REG(ndev, SMU_INTR_REG));  in aie2_smu_exec()
37 	writel(1, SMU_REG(ndev, SMU_INTR_REG));  in aie2_smu_exec()
39 	ret = readx_poll_timeout(readl, SMU_REG(ndev, SMU_RESP_REG), resp,  in aie2_smu_exec()
42 		XDNA_ERR(ndev->xdna, "smu cmd %d timed out", reg_cmd);  in aie2_smu_exec()
47 		*out = readl(SMU_REG(ndev, SMU_OUT_REG));  in aie2_smu_exec()
50 		XDNA_ERR(ndev->xdna, "smu cmd %d failed, 0x%x", reg_cmd, resp);  in aie2_smu_exec()
57 int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)  in npu1_set_dpm()  argument
62 	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_MPNPUCLK_FREQ,  in npu1_set_dpm()
63 			    ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq);  in npu1_set_dpm()
65 		XDNA_ERR(ndev->xdna, "Set npu clock to %d failed, ret %d\n",  in npu1_set_dpm()
66 			 ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret);  in npu1_set_dpm()
69 	ndev->npuclk_freq = freq;  in npu1_set_dpm()
71 	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HCLK_FREQ,  in npu1_set_dpm()
72 			    ndev->priv->dpm_clk_tbl[dpm_level].hclk, &freq);  in npu1_set_dpm()
74 		XDNA_ERR(ndev->xdna, "Set h clock to %d failed, ret %d\n",  in npu1_set_dpm()
75 			 ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret);  in npu1_set_dpm()
78 	ndev->hclk_freq = freq;  in npu1_set_dpm()
79 	ndev->dpm_level = dpm_level;  in npu1_set_dpm()
81 	XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",  in npu1_set_dpm()
82 		 ndev->npuclk_freq, ndev->hclk_freq);  in npu1_set_dpm()
87 int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)  in npu4_set_dpm()  argument
91 	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL);  in npu4_set_dpm()
93 		XDNA_ERR(ndev->xdna, "Set hard dpm level %d failed, ret %d ",  in npu4_set_dpm()
98 	ret = aie2_smu_exec(ndev, AIE2_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL);  in npu4_set_dpm()
100 		XDNA_ERR(ndev->xdna, "Set soft dpm level %d failed, ret %d",  in npu4_set_dpm()
105 	ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;  in npu4_set_dpm()
106 	ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;  in npu4_set_dpm()
107 	ndev->dpm_level = dpm_level;  in npu4_set_dpm()
109 	XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",  in npu4_set_dpm()
110 		 ndev->npuclk_freq, ndev->hclk_freq);  in npu4_set_dpm()
115 int aie2_smu_init(struct amdxdna_dev_hdl *ndev)  in aie2_smu_init()  argument
119 	ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_ON, 0, NULL);  in aie2_smu_init()
121 		XDNA_ERR(ndev->xdna, "Power on failed, ret %d", ret);  in aie2_smu_init()
128 void aie2_smu_fini(struct amdxdna_dev_hdl *ndev)  in aie2_smu_fini()  argument
132 	ndev->priv->hw_ops.set_dpm(ndev, 0);  in aie2_smu_fini()
133 	ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL);  in aie2_smu_fini()
135 		XDNA_ERR(ndev->xdna, "Power off failed, ret %d", ret);  in aie2_smu_fini()