Lines Matching +full:non +full:- +full:live

4  * Xtensa processor configuration-specific table of coprocessor and
11  * Copyright (C) 2003 - 2007 Tensilica Inc.
16 #include <asm/asm-offsets.h>
25  * - a task may have live coprocessors only on one CPU.
27  * - whether coprocessor context of task T is live on some CPU is
28  *   denoted by T's thread_info->cpenable.
30  * - non-zero thread_info->cpenable means that thread_info->cp_owner_cpu
31  *   is valid in the T's thread_info. Zero thread_info->cpenable means that
34  * - if a coprocessor context of task T is live on CPU X, only CPU X changes
35  *   T's thread_info->cpenable, cp_owner_cpu and coprocessor save area.
36  *   This is done by making sure that for the task T with live coprocessor
39  *   C-level do_coprocessor that uses IPI to make CPU X flush T's coprocessors.
128 	 * Check if any coprocessor context is live on another CPU
129 	 * and if so go through the C-level coprocessor exception handler
152 	/* Save remaining registers a1-a3 and SAR */
175 	addi	a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
177 	/* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
179 	ssl	a3			# SAR: 32 - coprocessor_number