1 // SPDX-License-Identifier: GPL-2.0-only
14  * pci_platform_pm_ops (see drivers/pci/pci-mid.c).
27 #include <asm/intel-mid.h>
108 	return readl(pwr->regs + PM_SSS(reg));  in mid_pwr_get_state()
113 	writel(value, pwr->regs + PM_SSC(reg));  in mid_pwr_set_state()
118 	writel(value, pwr->regs + PM_WKC(reg));  in mid_pwr_set_wake()
123 	writel(~PM_ICS_IE, pwr->regs + PM_ICS);  in mid_pwr_interrupt_disable()
128 	return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);  in mid_pwr_is_busy()
142 	} while (--count);  in mid_pwr_wait()
144 	return -EBUSY;  in mid_pwr_wait()
149 	writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);  in mid_pwr_wait_for_cmd()
168 	/* Send command to SCU */  in __update_power_state()
177 		return -EAGAIN;  in __update_power_state()
200 		dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");  in __find_weakest_power_state()
219 	state = __find_weakest_power_state(pwr->lss[id], pdev, state);  in __set_power_state()
224 		dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);  in __set_power_state()
228 	dev_vdbg(&pdev->dev, "Set power state %s\n", name);  in __set_power_state()
251 	mutex_lock(&pwr->lock);  in mid_pwr_set_power_state()
253 	mutex_unlock(&pwr->lock);  in mid_pwr_set_power_state()
264 	if (pwr && pwr->available)  in intel_mid_pci_set_power_state()
266 	dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);  in intel_mid_pci_set_power_state()
277 	if (!pwr || !pwr->available)  in intel_mid_pci_get_power_state()
299 	/* Send command to SCU */  in intel_mid_pwr_power_off()
300 	writel(cmd, pwr->regs + PM_CMD);  in intel_mid_pwr_power_off()
310 	 * Mapping to PWRMU index is kept in the Logical SubSystem ID byte of  in intel_mid_pwr_get_lss_id()
315 		return -EINVAL;  in intel_mid_pwr_get_lss_id()
320 		return -ENODEV;  in intel_mid_pwr_get_lss_id()
324 		return -ERANGE;  in intel_mid_pwr_get_lss_id()
334 	ics = readl(pwr->regs + PM_ICS);  in mid_pwr_irq_handler()
338 	writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);  in mid_pwr_irq_handler()
340 	dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));  in mid_pwr_irq_handler()
350 	struct mid_pwr_device_info *info = (void *)id->driver_data;  in mid_pwr_probe()
351 	struct device *dev = &pdev->dev;  in mid_pwr_probe()
357 		dev_err(&pdev->dev, "error: could not enable device\n");  in mid_pwr_probe()
363 		return -ENOMEM;  in mid_pwr_probe()
365 	pwr->regs = pcim_iomap_region(pdev, 0, "intel_mid_pwr");  in mid_pwr_probe()
366 	ret = PTR_ERR_OR_ZERO(pwr->regs);  in mid_pwr_probe()
368 		dev_err(&pdev->dev, "Could not request / ioremap I/O-Mem: %d\n", ret);  in mid_pwr_probe()
372 	pwr->dev = dev;  in mid_pwr_probe()
373 	pwr->irq = pdev->irq;  in mid_pwr_probe()
375 	mutex_init(&pwr->lock);  in mid_pwr_probe()
380 	if (info && info->set_initial_state) {  in mid_pwr_probe()
381 		ret = info->set_initial_state(pwr);  in mid_pwr_probe()
386 	ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,  in mid_pwr_probe()
391 	pwr->available = true;  in mid_pwr_probe()
416 	 * on 32-bit HW registers. The following calls set all devices to one  in mid_set_initial_state()
428 	/* Send command to SCU */  in mid_set_initial_state()
435 			pwr->lss[i][j].state = PCI_D3hot;  in mid_set_initial_state()
472 /* This table should be in sync with the one in drivers/pci/pci-mid.c */