Lines Matching +full:0 +full:x1401
25 reg = 0xd0; in pci_fixup_i450nx()
26 for(pxb = 0; pxb < 2; pxb++) { in pci_fixup_i450nx()
48 pci_read_config_byte(d, 0x4a, &busno); in pci_fixup_i450gx()
64 for(i = 0; i < 4; i++) in pci_fixup_umc_ide()
100 * - bits 5, 6, 7 at offset 0x55 need to be turned off
102 * - bits 5, 6, 7 at offset 0x95 need to be turned off
103 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
104 * - bits 6, 7 at offset 0x55 need to be turned off
107 #define VIA_8363_KL133_REVISION_ID 0x81
108 #define VIA_8363_KM133_REVISION_ID 0x84
113 int where = 0x55; in pci_fixup_via_northbridge_bug()
114 int mask = 0x1f; /* clear bits 5, 6, 7 by default */ in pci_fixup_via_northbridge_bug()
120 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0); in pci_fixup_via_northbridge_bug()
122 where = 0x95; /* the memory write queue timer register is in pci_fixup_via_northbridge_bug()
123 different for the KT266x's: 0x95 not 0x55 */ in pci_fixup_via_northbridge_bug()
127 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 in pci_fixup_via_northbridge_bug()
159 if ((dev->device & 0xff00) == 0x2400) in pci_fixup_transparent_bridge()
183 * C17 0x1F0FFF01 0x1F01FF01 in pci_fixup_nforce2()
184 * C18D 0x9F0FFF01 0x9F01FF01 in pci_fixup_nforce2()
187 * reading the PCI revision ID (0xC1 or greater is C18D). in pci_fixup_nforce2()
189 pci_read_config_dword(dev, 0x6c, &val); in pci_fixup_nforce2()
194 if ((val & 0x00FF0000) != 0x00010000) { in pci_fixup_nforce2()
196 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); in pci_fixup_nforce2()
269 for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) in pcie_rootport_aspm_quirk()
270 quirk_aspm_offset[i] = 0; in pcie_rootport_aspm_quirk()
281 /* There are 0 to 8 devices attached to this bus */ in pcie_rootport_aspm_quirk()
304 * card will have its BIOS copied to 0xC0000 in system RAM.
350 res->start = 0xC0000; in pci_fixup_video()
351 res->end = res->start + 0x20000 - 1; in pci_fixup_video()
390 pci_read_config_byte(dev, 0x50, &val); in pci_fixup_msi_k8t_onboard_sound()
391 if (val & 0x40) { in pci_fixup_msi_k8t_onboard_sound()
392 pci_write_config_byte(dev, 0x50, val & (~0x40)); in pci_fixup_msi_k8t_onboard_sound()
395 pci_read_config_byte(dev, 0x50, &val); in pci_fixup_msi_k8t_onboard_sound()
396 if (val & 0x40) in pci_fixup_msi_k8t_onboard_sound()
453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
465 pci_resource_start(dev, 0)); in pci_post_fixup_toshiba_ohci1394()
469 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
481 pci_read_config_byte(dev, 0x42, &r); in pci_early_fixup_cyrix_5530()
482 r &= 0xfd; in pci_early_fixup_cyrix_5530()
483 pci_write_config_byte(dev, 0x42, r); in pci_early_fixup_cyrix_5530()
496 dev->resource[0].flags |= IORESOURCE_PCI_FIXED; in pci_siemens_interrupt_controller()
498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
511 * ID, but the PM register 0x55 does something different in sb600_disable_hpet_bar()
516 pci_read_config_byte(dev, 0x08, &val); in sb600_disable_hpet_bar()
518 if (val < 0x2F) { in sb600_disable_hpet_bar()
519 outb(0x55, 0xCD6); in sb600_disable_hpet_bar()
520 val = inb(0xCD7); in sb600_disable_hpet_bar()
522 /* Set bit 7 in PM register 0x55 */ in sb600_disable_hpet_bar()
523 outb(0x55, 0xCD6); in sb600_disable_hpet_bar()
524 outb(val | 0x80, 0xCD7); in sb600_disable_hpet_bar()
527 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
536 dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n"); in sb600_hpet_quirk()
539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk);
552 if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) { in twinhead_reserve_killing_zone()
554 request_mem_region(0xFFB00000, 0x100000, "twinhead"); in twinhead_reserve_killing_zone()
557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
574 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar);
575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar);
576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar);
577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar);
578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ec, pci_invalid_bar);
579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ed, pci_invalid_bar);
580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26c, pci_invalid_bar);
581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26d, pci_invalid_bar);
596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);
607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);
610 * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
612 * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to
613 * the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used
629 pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x1c, 0)) in quirk_apple_mbp_poweroff()
632 res = request_mem_region(0x7fa00000, 0x200000, in quirk_apple_mbp_poweroff()
639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
664 if (r->end == r->start + 0x7ff) { in quirk_intel_th_dnv()
665 r->start = 0; in quirk_intel_th_dnv()
666 r->end = 0x3fffff; in quirk_intel_th_dnv()
670 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv);
674 #define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8)
675 #define AMD_141b_MMIO_BASE_RE_MASK BIT(0)
679 #define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8)
682 #define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4)
683 #define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0)
715 for (i = 0; i < 8; i++) { in pci_amd_enable_64bit_bar()
728 if (base > 0x10000) in pci_amd_enable_64bit_bar()
739 * Allocate a 256GB window directly below the 0xfd00000000 hardware in pci_amd_enable_64bit_bar()
745 res->start = 0xbd00000000ull; in pci_amd_enable_64bit_bar()
746 res->end = 0xfd00000000ull - 1; in pci_amd_enable_64bit_bar()
774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
776 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
779 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
780 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
781 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
782 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
783 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
785 #define RS690_LOWER_TOP_OF_DRAM2 0x30
786 #define RS690_LOWER_TOP_OF_DRAM2_VALID 0x1
787 #define RS690_UPPER_TOP_OF_DRAM2 0x31
788 #define RS690_HTIU_NB_INDEX 0xA8
789 #define RS690_HTIU_NB_INDEX_WR_ENABLE 0x100
790 #define RS690_HTIU_NB_DATA 0xAC
803 u32 val = 0; in rs690_fix_64bit_dma()
827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
833 #define AMD_15B8_RCC_DEV2_EPF0_STRAP2 0x10136008
834 #define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L
840 if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) { in quirk_clear_strap_no_soft_reset_dev2_f0()
842 if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data)) in quirk_clear_strap_no_soft_reset_dev2_f0()
843 pci_err(dev, "Failed to write data 0x%x\n", data); in quirk_clear_strap_no_soft_reset_dev2_f0()
848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
865 int pos = PCI_CFG_SPACE_SIZE, prev = 0; in chromeos_save_apl_pci_l1ss_capability()
866 u32 header, pheader = 0; in chromeos_save_apl_pci_l1ss_capability()
907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
908 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);
921 * StorageD3Enable from 1 to 0.
953 if (dmi_check_system(asus_nvme_broken_d3cold_table) > 0) in asus_disable_nvme_d3cold()
956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x9a09, asus_disable_nvme_d3cold);
1004 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x162e, amd_rp_pme_suspend);
1005 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x162e, amd_rp_pme_resume);
1006 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x162f, amd_rp_pme_suspend);
1007 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x162f, amd_rp_pme_resume);
1009 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x1668, amd_rp_pme_suspend);
1010 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1668, amd_rp_pme_resume);
1011 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_AMD, 0x1669, amd_rp_pme_suspend);
1012 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1669, amd_rp_pme_resume);
1042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1502, quirk_tuxeo_rp_d3);