1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Copyright (C) 2000-2006 Tigran Aivazian <[email protected]>
63 	return hdr->datasize ? hdr->totalsize : DEFAULT_UCODE_TOTALSIZE;  in get_totalsize()
68 	return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;  in exttable_size()
73 	sig->sig = cpuid_eax(1);  in intel_collect_cpu_info()
74 	sig->pf = 0;  in intel_collect_cpu_info()
75 	sig->rev = intel_get_microcode_revision();  in intel_collect_cpu_info()
77 	if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) {  in intel_collect_cpu_info()
82 		sig->pf = 1 << ((val[1] >> 18) & 7);  in intel_collect_cpu_info()
90 	if (s1->sig != sig2)  in cpu_signatures_match()
94 	return ((!s1->pf && !pf2) || (s1->pf & pf2));  in cpu_signatures_match()
104 	if (cpu_signatures_match(sig, mc_hdr->sig, mc_hdr->pf))  in intel_find_matching_signature()
114 	for (i = 0; i < ext_hdr->count; i++) {  in intel_find_matching_signature()
115 		if (cpu_signatures_match(sig, ext_sig->sig, ext_sig->pf))  in intel_find_matching_signature()
124  * intel_microcode_sanity_check() - Sanity check microcode file.
134  * Return: 0 if the file passes all the checks, -EINVAL if any of the checks
151 		return -EINVAL;  in intel_microcode_sanity_check()
154 	if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) {  in intel_microcode_sanity_check()
157 			       mc_header->hdrver);  in intel_microcode_sanity_check()
158 		return -EINVAL;  in intel_microcode_sanity_check()
161 	ext_table_size = total_size - (MC_HEADER_SIZE + data_size);  in intel_microcode_sanity_check()
167 		    ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {  in intel_microcode_sanity_check()
170 			return -EINVAL;  in intel_microcode_sanity_check()
177 			return -EFAULT;  in intel_microcode_sanity_check()
180 		ext_sigcount = ext_header->count;  in intel_microcode_sanity_check()
189 		while (i--)  in intel_microcode_sanity_check()
195 			return -EINVAL;  in intel_microcode_sanity_check()
206 	while (i--)  in intel_microcode_sanity_check()
212 		return -EINVAL;  in intel_microcode_sanity_check()
225 		sum = (mc_header->sig + mc_header->pf + mc_header->cksum) -  in intel_microcode_sanity_check()
226 		      (ext_sig->sig + ext_sig->pf + ext_sig->cksum);  in intel_microcode_sanity_check()
230 			return -EINVAL;  in intel_microcode_sanity_check()
250 	unsigned int size = get_totalsize(&patch->hdr);  in save_microcode_patch()
267 	u32 cur_rev = uci->cpu_sig.rev;  in scan_microcode()
270 	for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) {  in scan_microcode()
278 		if (!intel_find_matching_signature(data, &uci->cpu_sig))  in scan_microcode()
289 			if (cur_rev != mc_header->rev)  in scan_microcode()
291 		} else if (cur_rev >= mc_header->rev) {  in scan_microcode()
296 		cur_rev = mc_header->rev;  in scan_microcode()
312 	 * Save us the MSR write below - which is a particular expensive  in __apply_microcode()
313 	 * operation - when the other hyperthread has updated the microcode  in __apply_microcode()
317 	if (*cur_rev >= mc->hdr.rev) {  in __apply_microcode()
318 		uci->cpu_sig.rev = *cur_rev;  in __apply_microcode()
323 	native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);  in __apply_microcode()
326 	if (rev != mc->hdr.rev)  in __apply_microcode()
329 	uci->cpu_sig.rev = rev;  in __apply_microcode()
335 	struct microcode_intel *mc = uci->mc;  in apply_microcode_early()
343 	unsigned int eax = 1, ebx, ecx = 0, edx;  in load_builtin_intel_microcode()  local
350 	native_cpuid(&eax, &ebx, &ecx, &edx);  in load_builtin_intel_microcode()
352 	sprintf(name, "intel-ucode/%02x-%02x-%02x",  in load_builtin_intel_microcode()
356 		cp->size = fw.size;  in load_builtin_intel_microcode()
357 		cp->data = (void *)fw.data;  in load_builtin_intel_microcode()
367 	intel_collect_cpu_info(&uci->cpu_sig);  in get_microcode_blob()
408 	ed->old_rev = uci.cpu_sig.rev;  in load_ucode_intel_bsp()
412 		ed->new_rev = uci.cpu_sig.rev;  in load_ucode_intel_bsp()
454 	cpu_data(cpu).microcode	 = uci->cpu_sig.rev;  in apply_microcode_late()
456 		boot_cpu_data.microcode = uci->cpu_sig.rev;  in apply_microcode_late()
466 	 * When late-loading, ensure the header declares a minimum revision  in ucode_validate_minrev()
467 	 * required to perform a late-load. The previously reserved field  in ucode_validate_minrev()
470 	if (!mc_header->min_req_ver) {  in ucode_validate_minrev()
479 	if (cur_rev < mc_header->min_req_ver) {  in ucode_validate_minrev()
481 …pr_info("Current should be at 0x%x or higher. Use early loading instead\n", mc_header->min_req_ver…  in ucode_validate_minrev()
491 	int cur_rev = uci->cpu_sig.rev;  in parse_microcode_blobs()
510 		data_size = mc_size - sizeof(mc_header);  in parse_microcode_blobs()
534 		if (!intel_find_matching_signature(mc, &uci->cpu_sig))  in parse_microcode_blobs()
572 	 * Processor E7-8800/4800 v4 Product Family).  in is_blacklisted()
574 	if (c->x86_vfm == INTEL_BROADWELL_X &&  in is_blacklisted()
575 	    c->x86_stepping == 0x01 &&  in is_blacklisted()
577 	    c->microcode < 0x0b000021) {  in is_blacklisted()
578 …pr_err_once("Erratum BDX90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microc…  in is_blacklisted()
579 …pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS upda…  in is_blacklisted()
598 	sprintf(name, "intel-ucode/%02x-%02x-%02x",  in request_microcode_fw()
599 		c->x86, c->x86_model, c->x86_stepping);  in request_microcode_fw()
606 	kvec.iov_base = (void *)firmware->data;  in request_microcode_fw()
607 	kvec.iov_len = firmware->size;  in request_microcode_fw()
608 	iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size);  in request_microcode_fw()
635 	u64 llc_size = c->x86_cache_size * 1024ULL;  in calc_llc_size_per_core()
645 	if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||  in init_intel_microcode()
647 		pr_err("Intel CPU family 0x%x not supported\n", c->x86);  in init_intel_microcode()