Lines Matching +full:high +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
52 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
139 if (!b->hwid) in smca_get_bank_type()
142 return b->hwid->bank_type; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
234 /* Value upon which threshold interrupt is generated. */
238 /* List of threshold blocks within this block's MCA bank. */
269 u32 low, high; in smca_set_misc_banks_map() local
273 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). in smca_set_misc_banks_map()
275 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
281 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
294 u32 high, low; in smca_configure() local
298 if (!rdmsr_safe(smca_config, &low, &high)) { in smca_configure()
306 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) in smca_configure()
308 high |= BIT(0); in smca_configure()
317 * high portion of the MSR). OS should set this to 0x1 to enable in smca_configure()
321 if ((low & BIT(5)) && !((high >> 5) & 0x3)) in smca_configure()
322 high |= BIT(5); in smca_configure()
326 wrmsr(smca_config, low, high); in smca_configure()
331 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { in smca_configure()
336 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, in smca_configure()
337 (high & MCI_IPID_MCATYPE) >> 16); in smca_configure()
342 if (hwid_mcatype == s_hwid->hwid_mcatype) { in smca_configure()
345 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++; in smca_configure()
361 switch (b->address) { in bank4_names()
373 WARN(1, "Funny MSR: 0x%08x\n", b->address); in bank4_names()
399 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " in lvt_off_valid()
400 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, in lvt_off_valid()
401 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
414 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " in lvt_off_valid()
416 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
423 /* Reprogram MCx_MISC MSR behind this threshold bank. */
430 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) in threshold_restart_bank()
433 rdmsr(tr->b->address, lo, hi); in threshold_restart_bank()
435 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) in threshold_restart_bank()
436 tr->reset = 1; /* limit cannot be lower than err count */ in threshold_restart_bank()
438 if (tr->reset) { /* reset err count and overflow bit */ in threshold_restart_bank()
441 (THRESHOLD_MAX - tr->b->threshold_limit); in threshold_restart_bank()
442 } else if (tr->old_limit) { /* change limit w/o reset */ in threshold_restart_bank()
444 (tr->old_limit - tr->b->threshold_limit); in threshold_restart_bank()
453 if (!tr->b->interrupt_capable) in threshold_restart_bank()
456 if (tr->set_lvt_off) { in threshold_restart_bank()
457 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { in threshold_restart_bank()
460 hi |= tr->lvt_off << 20; in threshold_restart_bank()
464 if (tr->b->interrupt_enable) in threshold_restart_bank()
470 wrmsr(tr->b->address, lo, hi); in threshold_restart_bank()
481 b->threshold_limit = THRESHOLD_MAX; in mce_threshold_block_init()
505 u32 low = 0, high = 0; in deferred_error_interrupt_enable() local
506 int def_offset = -1, def_new; in deferred_error_interrupt_enable()
508 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) in deferred_error_interrupt_enable()
526 wrmsr(MSR_CU_DEF_ERR, low, high); in deferred_error_interrupt_enable()
538 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); in smca_get_block_address()
541 static u32 get_block_address(u32 current_addr, u32 low, u32 high, in get_block_address() argument
618 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); in amd_filter_mce()
621 /* See Family 17h Models 10h-2Fh Erratum #1114. */ in amd_filter_mce()
622 if (c->x86 == 0x17 && in amd_filter_mce()
623 c->x86_model >= 0x10 && c->x86_model <= 0x2F && in amd_filter_mce()
624 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) in amd_filter_mce()
628 if (c->x86 < 0x17) { in amd_filter_mce()
629 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5) in amd_filter_mce()
638 * - MC4_MISC thresholding is not supported on Family 0x15.
639 * - Prevent possible spurious interrupts from the IF bank on Family 0x17
640 * Models 0x10-0x2F due to Erratum #1114.
649 if (c->x86 == 0x15 && bank == 4) { in disable_err_thresholding()
653 } else if (c->x86 == 0x17 && in disable_err_thresholding()
654 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { in disable_err_thresholding()
685 u32 low = 0, high = 0, address = 0; in mce_amd_feature_init() local
686 int offset = -1; in mce_amd_feature_init()
696 address = get_block_address(address, low, high, bank, block, cpu); in mce_amd_feature_init()
700 if (rdmsr_safe(address, &low, &high)) in mce_amd_feature_init()
703 if (!(high & MASK_VALID_HI)) in mce_amd_feature_init()
706 if (!(high & MASK_CNTP_HI) || in mce_amd_feature_init()
707 (high & MASK_LOCKED_HI)) in mce_amd_feature_init()
710 offset = prepare_threshold_block(bank, block, address, offset, high); in mce_amd_feature_init()
724 return m->bank == 4 && XEC(m->status, 0x1f) == 8; in legacy_mce_is_memory_error()
735 if (XEC(m->status, 0x3f)) in smca_mce_is_memory_error()
738 bank_type = smca_get_bank_type(m->extcpu, m->bank); in smca_mce_is_memory_error()
777 else if (m->bank == 4) in amd_mce_usable_address()
782 if (m->status & MCI_STATUS_POISON) in amd_mce_usable_address()
796 m->status = status; in __log_error()
797 m->misc = misc; in __log_error()
798 m->bank = bank; in __log_error()
799 m->tsc = rdtsc(); in __log_error()
801 if (m->status & MCI_STATUS_ADDRV) { in __log_error()
802 m->addr = addr; in __log_error()
808 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m->ipid); in __log_error()
810 if (m->status & MCI_STATUS_SYNDV) { in __log_error()
811 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m->synd); in __log_error()
858 * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. in _log_error_deferred()
872 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
908 u32 low = 0, high = 0; in log_and_reset_block() local
913 if (rdmsr_safe(block->address, &low, &high)) in log_and_reset_block()
916 if (!(high & MASK_OVERFLOW_HI)) in log_and_reset_block()
919 /* Log the MCE which caused the threshold event. */ in log_and_reset_block()
920 log_error_thresholding(block->bank, ((u64)high << 32) | low); in log_and_reset_block()
922 /* Reset threshold block after logging error. */ in log_and_reset_block()
929 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
939 * Validate that the threshold bank has been initialized already. The in amd_threshold_interrupt()
950 first_block = bp[bank]->blocks; in amd_threshold_interrupt()
959 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) in amd_threshold_interrupt()
977 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
988 if (!b->interrupt_capable) in SHOW_FIELDS()
989 return -EINVAL; in SHOW_FIELDS()
992 return -EINVAL; in SHOW_FIELDS()
994 b->interrupt_enable = !!new; in SHOW_FIELDS()
999 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) in SHOW_FIELDS()
1000 return -ENODEV; in SHOW_FIELDS()
1012 return -EINVAL; in store_threshold_limit()
1020 tr.old_limit = b->threshold_limit; in store_threshold_limit()
1021 b->threshold_limit = new; in store_threshold_limit()
1024 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1)) in store_threshold_limit()
1025 return -ENODEV; in store_threshold_limit()
1035 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) in show_error_count()
1036 return -ENODEV; in show_error_count()
1038 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - in show_error_count()
1039 (THRESHOLD_MAX - b->threshold_limit))); in show_error_count()
1074 ret = a->show ? a->show(b, buf) : -EIO; in show()
1086 ret = a->store ? a->store(b, buf, count) : -EIO; in store()
1120 if (b->block < ARRAY_SIZE(smca_umc_block_names)) in get_name()
1121 return smca_umc_block_names[b->block]; in get_name()
1139 u32 low, high; in allocate_threshold_blocks() local
1145 if (rdmsr_safe(address, &low, &high)) in allocate_threshold_blocks()
1148 if (!(high & MASK_VALID_HI)) { in allocate_threshold_blocks()
1155 if (!(high & MASK_CNTP_HI) || in allocate_threshold_blocks()
1156 (high & MASK_LOCKED_HI)) in allocate_threshold_blocks()
1161 return -ENOMEM; in allocate_threshold_blocks()
1163 b->block = block; in allocate_threshold_blocks()
1164 b->bank = bank; in allocate_threshold_blocks()
1165 b->cpu = cpu; in allocate_threshold_blocks()
1166 b->address = address; in allocate_threshold_blocks()
1167 b->interrupt_enable = 0; in allocate_threshold_blocks()
1168 b->interrupt_capable = lvt_interrupt_supported(bank, high); in allocate_threshold_blocks()
1169 b->threshold_limit = THRESHOLD_MAX; in allocate_threshold_blocks()
1171 if (b->interrupt_capable) { in allocate_threshold_blocks()
1173 b->interrupt_enable = 1; in allocate_threshold_blocks()
1178 INIT_LIST_HEAD(&b->miscj); in allocate_threshold_blocks()
1181 if (tb->blocks) in allocate_threshold_blocks()
1182 list_add(&b->miscj, &tb->blocks->miscj); in allocate_threshold_blocks()
1184 tb->blocks = b; in allocate_threshold_blocks()
1186 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b)); in allocate_threshold_blocks()
1190 address = get_block_address(address, low, high, bank, ++block, cpu); in allocate_threshold_blocks()
1199 kobject_uevent(&b->kobj, KOBJ_ADD); in allocate_threshold_blocks()
1205 list_del(&b->miscj); in allocate_threshold_blocks()
1206 kobject_put(&b->kobj); in allocate_threshold_blocks()
1220 return -ENODEV; in threshold_create_bank()
1224 err = -ENOMEM; in threshold_create_bank()
1228 /* Associate the bank with the per-CPU MCE device */ in threshold_create_bank()
1229 b->kobj = kobject_create_and_add(name, &dev->kobj); in threshold_create_bank()
1230 if (!b->kobj) { in threshold_create_bank()
1231 err = -EINVAL; in threshold_create_bank()
1243 kobject_put(b->kobj); in threshold_create_bank()
1259 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) { in deallocate_threshold_blocks()
1260 list_del(&pos->miscj); in deallocate_threshold_blocks()
1261 kobject_put(&pos->kobj); in deallocate_threshold_blocks()
1264 kobject_put(&bank->blocks->kobj); in deallocate_threshold_blocks()
1269 if (!bank->blocks) in threshold_remove_bank()
1275 kobject_put(bank->kobj); in threshold_remove_bank()
1311 * mce_threshold_create_device - Create the per-CPU MCE threshold device
1314 * Create directories and files for all valid threshold banks.
1337 return -ENOMEM; in mce_threshold_create_device()