Lines Matching +full:8 +full:k
264 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate in early_init_intel()
270 if (c->x86_power & (1 << 8)) { in early_init_intel()
356 boot_cpu_data.x86_stepping < 8) { in ppro_with_ram_bug()
416 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
448 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
462 case 6: /* PII/PIII only like movsl with 8-byte alignment */ in intel_workarounds()
465 case 15: /* P4 is OK down to 8-byte alignment */ in intel_workarounds()
535 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) in init_intel()
593 case 8: in init_intel()
630 * 16K cache with a 16 byte cache line and 256 lines per tag in intel_size_cache()
674 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
692 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
693 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
695 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
697 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
701 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
702 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
704 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
705 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
713 unsigned char k; in intel_tlb_lookup() local
718 for (k = 0; intel_tlb_table[k].descriptor != desc && in intel_tlb_lookup()
719 intel_tlb_table[k].descriptor != 0; k++) in intel_tlb_lookup()
722 if (intel_tlb_table[k].tlb_type == 0) in intel_tlb_lookup()
725 switch (intel_tlb_table[k].tlb_type) { in intel_tlb_lookup()
727 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
728 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
729 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
730 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
733 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
734 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
735 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
736 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
737 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
738 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
739 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
740 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
741 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
742 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
743 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
744 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
747 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
748 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
749 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
750 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
751 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
752 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
755 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
756 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
759 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
760 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
763 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
764 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
765 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
766 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
770 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
771 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
775 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
776 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
780 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
781 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
782 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
783 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
786 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
787 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
788 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
789 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
798 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
799 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
844 [8] = "486 DX/4",
856 [8] = "Mobile Pentium MMX",
869 [8] = "Pentium III (Coppermine)",