Lines Matching +full:0 +full:x86
79 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
114 { INTEL_KABYLAKE, 0x0B, 0x80 },
115 { INTEL_KABYLAKE, 0x0A, 0x80 },
116 { INTEL_KABYLAKE, 0x09, 0x80 },
117 { INTEL_KABYLAKE_L, 0x0A, 0x80 },
118 { INTEL_KABYLAKE_L, 0x09, 0x80 },
119 { INTEL_SKYLAKE_X, 0x03, 0x0100013e },
120 { INTEL_SKYLAKE_X, 0x04, 0x0200003c },
121 { INTEL_BROADWELL, 0x04, 0x28 },
122 { INTEL_BROADWELL_G, 0x01, 0x1b },
123 { INTEL_BROADWELL_D, 0x02, 0x14 },
124 { INTEL_BROADWELL_D, 0x03, 0x07000011 },
125 { INTEL_BROADWELL_X, 0x01, 0x0b000025 },
126 { INTEL_HASWELL_L, 0x01, 0x21 },
127 { INTEL_HASWELL_G, 0x01, 0x18 },
128 { INTEL_HASWELL, 0x03, 0x23 },
129 { INTEL_HASWELL_X, 0x02, 0x3b },
130 { INTEL_HASWELL_X, 0x04, 0x10 },
131 { INTEL_IVYBRIDGE_X, 0x04, 0x42a },
133 { INTEL_SANDYBRIDGE_X, 0x06, 0x61b },
134 { INTEL_SANDYBRIDGE_X, 0x07, 0x712 },
148 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { in bad_spectre_microcode()
156 #define MSR_IA32_TME_ACTIVATE 0x982
159 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
160 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
162 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
172 pr_info_once("x86/tme: not enabled by BIOS\n"); in detect_tme_early()
176 pr_info_once("x86/tme: enabled by BIOS\n"); in detect_tme_early()
189 pr_info_once("x86/mktme: BIOS enabled: x86_phys_bits reduced by %d\n", in detect_tme_early()
198 if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd)) in intel_unlock_cpuid_leafs()
205 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) in intel_unlock_cpuid_leafs()
206 c->cpuid_level = cpuid_eax(0); in intel_unlock_cpuid_leafs()
213 if ((c->x86 == 0xf && c->x86_model >= 0x03) || in early_init_intel()
214 (c->x86 == 0x6 && c->x86_model >= 0x0e)) in early_init_intel()
217 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
245 c->microcode < 0x20e) { in early_init_intel()
254 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
258 /* CPUID workaround for 0F33/0F34 CPU */ in early_init_intel()
259 if (c->x86 == 0xF && c->x86_model == 0x3 in early_init_intel()
260 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
304 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
319 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h in early_init_intel()
354 boot_cpu_data.x86 == 6 && in ppro_with_ram_bug()
360 return 0; in ppro_with_ram_bug()
372 if (c->x86 == 5 && in intel_smp_check()
396 * have the F0 0F bug, which lets nonprivileged users lock up the in intel_workarounds()
401 if (c->x86 == 5 && c->x86_model < 9) { in intel_workarounds()
406 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); in intel_workarounds()
416 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
434 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { in intel_workarounds()
436 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { in intel_workarounds()
448 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
449 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
457 switch (c->x86) { in intel_workarounds()
514 this_cpu_write(msr_misc_features_shadow, 0); in init_intel_misc_features()
535 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) in init_intel()
564 if (c->x86 == 15) in init_intel()
566 if (c->x86 == 6) in init_intel()
574 if (c->x86 == 6) { in init_intel()
580 if (l2 == 0) in init_intel()
589 else if (c->x86_stepping == 0 || c->x86_stepping == 5) in init_intel()
625 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) in intel_size_cache()
632 if ((c->x86 == 5) && (c->x86_model == 9)) in intel_size_cache()
638 #define TLB_INST_4K 0x01
639 #define TLB_INST_4M 0x02
640 #define TLB_INST_2M_4M 0x03
642 #define TLB_INST_ALL 0x05
643 #define TLB_INST_1G 0x06
645 #define TLB_DATA_4K 0x11
646 #define TLB_DATA_4M 0x12
647 #define TLB_DATA_2M_4M 0x13
648 #define TLB_DATA_4K_4M 0x14
650 #define TLB_DATA_1G 0x16
651 #define TLB_DATA_1G_2M_4M 0x17
653 #define TLB_DATA0_4K 0x21
654 #define TLB_DATA0_4M 0x22
655 #define TLB_DATA0_2M_4M 0x23
657 #define STLB_4K 0x41
658 #define STLB_4K_2M 0x42
661 * All of leaf 0x2's one-byte TLB descriptors implies the same number of
662 * entries for their respective TLB types. The 0x63 descriptor is an
664 * for 2MB or 4MB pages. Encode descriptor 0x63 dTLB entry count for
671 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
672 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
673 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
674 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
675 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
676 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
677 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
678 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
679 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
680 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
681 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
682 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
683 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
684 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
685 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
686 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
687 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
688 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
689 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
690 { 0x63, TLB_DATA_1G_2M_4M, 4, " TLB_DATA 1 GByte pages, 4-way set associative"
692 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
693 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
694 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
695 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
696 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
697 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
698 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
699 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
700 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
701 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
702 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
703 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
704 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
705 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
706 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
707 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
708 { 0x00, 0, 0 }
714 if (desc == 0) in intel_tlb_lookup()
718 for (k = 0; intel_tlb_table[k].descriptor != desc && in intel_tlb_lookup()
719 intel_tlb_table[k].descriptor != 0; k++) in intel_tlb_lookup()
722 if (intel_tlb_table[k].tlb_type == 0) in intel_tlb_lookup()
814 n = cpuid_eax(2) & 0xFF; in intel_detect_tlb()
816 for (i = 0 ; i < n ; i++) { in intel_detect_tlb()
817 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); in intel_detect_tlb()
820 for (j = 0 ; j < 4 ; j++) in intel_detect_tlb()
822 regs[j] = 0; in intel_detect_tlb()
824 /* Byte 0 is level count, not a descriptor */ in intel_detect_tlb()
837 [0] = "486 DX-25/33",
850 [0] = "Pentium 60/66 A-step",
862 [0] = "Pentium Pro A-step",
876 [0] = "Pentium 4 (Unknown)",
901 * a hybrid processor. If the processor is not hybrid, returns 0.
906 return 0; in get_this_hybrid_cpu_type()
908 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; in get_this_hybrid_cpu_type()
914 * Returns the uarch native ID [23:0] of a CPU in a hybrid processor.
915 * If the processor is not hybrid, returns 0.
920 return 0; in get_this_hybrid_cpu_native_id()
922 return cpuid_eax(0x0000001a) & in get_this_hybrid_cpu_native_id()