Lines Matching +full:4 +full:mb
6 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
33 #define LVL_3 4
53 #define MB(x) ((x) * 1024) macro
60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
68 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
69 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
70 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
71 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
74 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
77 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
79 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
81 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
82 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
83 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
84 { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
85 { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
86 { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
87 { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
88 { 0x48, LVL_2, MB(3) }, /* 12-way set assoc, 64 byte line size */
89 { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
90 { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
91 { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
92 { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
93 { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
94 { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
96 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
97 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
98 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
103 { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
107 { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
108 { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
113 { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
114 { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
115 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
116 { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
117 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
118 { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
119 { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
120 { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
121 { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
122 { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
123 { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
124 { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
125 { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
126 { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
127 { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
128 { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
129 { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
130 { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
131 { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
149 unsigned int reserved:4;
200 unsigned lines_per_tag:4;
201 unsigned assoc:4;
210 unsigned lines_per_tag:4;
211 unsigned assoc:4;
221 [4] = 4,
329 l3->subcaches[1] = sc1 = !(val & BIT(4)); in amd_calc_l3_indices()
353 pci_read_config_dword(nb->misc, 0x1BC + slot * 4, ®); in amd_get_l3_disable_slot()
394 * disable index in all 4 subcaches in amd_l3_disable_index()
396 for (i = 0; i < 4; i++) { in amd_l3_disable_index()
402 pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); in amd_l3_disable_index()
412 pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg); in amd_l3_disable_index()
625 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx); in cpuid4_cache_lookup_regs()
651 op = 4; in find_num_cache_leaves()
724 ci->num_leaves = 4; in init_amd_cacheinfo()
741 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ in init_intel_cacheinfo()
742 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */ in init_intel_cacheinfo()
755 * Whenever possible use cpuid(4), deterministic cache in init_intel_cacheinfo()
797 unsigned int regs[4]; in init_intel_cacheinfo()
811 for (j = 0 ; j < 4 ; j++) in init_intel_cacheinfo()
867 * If llc_id is not yet set, this means cpuid_level < 4 which in in init_intel_cacheinfo()
1005 * The max shared threads number comes from CPUID.4:EAX[25-14] with input