1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * AMD Node helper functions and common defines
17  * The nodes are software-visible through PCI config space. All nodes are enumerated
19  * nodes) with 0x18 corresponding to node 0, 0x19 to node 1, etc. Each node can be a
20  * multi-function device.
22  * On legacy systems, these node devices represent integrated Northbridge functionality.
23  * On Zen-based systems, these node devices represent Data Fabric functionality.
26  * "Processor x86 Core" -> "Configuration Space" section in PPRs.
28 struct pci_dev *amd_node_get_func(u16 node, u8 func)  in amd_node_get_func()  argument
30 	if (node >= MAX_AMD_NUM_NODES)  in amd_node_get_func()
33 	return pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(AMD_NODE0_PCI_SLOT + node, func));  in amd_node_get_func()
49 	 * Major revision of '0' is found pre-DF4. Field is Read-as-Zero.  in get_cfg_addr_cntl_offset()
60 struct pci_dev *amd_node_get_root(u16 node)  in amd_node_get_root()  argument
62 	struct pci_dev *root;  in amd_node_get_root()  local
71 	 * Bits [7:0] (SecBusNum) holds the bus number of the root device for  in amd_node_get_root()
74 	struct pci_dev *df_f0 __free(pci_dev_put) = amd_node_get_func(node, 0);  in amd_node_get_root()
85 	/* Grab the pointer for the actual root device instance. */  in amd_node_get_root()
86 	root = pci_get_domain_bus_and_slot(0, bus, 0);  in amd_node_get_root()
88 	pci_dbg(root, "is root for AMD node %u\n", node);  in amd_node_get_root()
89 	return root;  in amd_node_get_root()
105  * For SMN reads, the returned value may be zero if the register is Read-as-Zero.
109  * But the Read-as-Zero response cannot be verified here. A value of 0 may be
118  * 1) Bits that are "Write-1-to-Clear". In this case, the read value should
121  * 2) Bits that are "Read-as-Zero"/"Writes-Ignored". This information cannot be
137 static int __amd_smn_rw(u8 i_off, u8 d_off, u16 node, u32 address, u32 *value, bool write)  in __amd_smn_rw()  argument
139 	struct pci_dev *root;  in __amd_smn_rw()  local
140 	int err = -ENODEV;  in __amd_smn_rw()
142 	if (node >= amd_num_nodes())  in __amd_smn_rw()
145 	root = amd_roots[node];  in __amd_smn_rw()
146 	if (!root)  in __amd_smn_rw()
151 	err = pci_write_config_dword(root, i_off, address);  in __amd_smn_rw()
157 	err = (write ? pci_write_config_dword(root, d_off, *value)  in __amd_smn_rw()
158 		     : pci_read_config_dword(root, d_off, value));  in __amd_smn_rw()
163 int __must_check amd_smn_read(u16 node, u32 address, u32 *value)  in amd_smn_read()  argument
165 	int err = __amd_smn_rw(SMN_INDEX_OFFSET, SMN_DATA_OFFSET, node, address, value, false);  in amd_smn_read()
168 		err = -ENODEV;  in amd_smn_read()
176 int __must_check amd_smn_write(u16 node, u32 address, u32 value)  in amd_smn_write()  argument
178 	return __amd_smn_rw(SMN_INDEX_OFFSET, SMN_DATA_OFFSET, node, address, &value, true);  in amd_smn_write()
184 	u16 node, num_nodes = amd_num_nodes();  in amd_cache_roots()  local
188 		return -ENOMEM;  in amd_cache_roots()
190 	for (node = 0; node < num_nodes; node++)  in amd_cache_roots()
191 		amd_roots[node] = amd_node_get_root(node);  in amd_cache_roots()