Lines Matching +full:0 +full:x4321
71 #define UV2 (1 << 0)
78 #define UV_ANY (~0)
85 #define UV1_HUB_PART_NUMBER 0x88a5
86 #define UV2_HUB_PART_NUMBER 0x8eb8
87 #define UV2_HUB_PART_NUMBER_X 0x1111
88 #define UV3_HUB_PART_NUMBER 0x9578
89 #define UV3_HUB_PART_NUMBER_X 0x4321
90 #define UV4_HUB_PART_NUMBER 0x99a1
91 #define UV5_HUB_PART_NUMBER 0xa171
99 #define UVH_EVENT_OCCURRED0 0x70000UL
102 #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
103 #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
107 #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
109 #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
111 #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
113 #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
115 #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
117 #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
119 #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
121 #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
123 #define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
125 #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
127 #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
129 #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
131 #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
133 #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
137 #define UVYH_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL
139 #define UVYH_EVENT_OCCURRED0_RH0_HCERR_MASK 0x0000000000000004UL
141 #define UVYH_EVENT_OCCURRED0_RH1_HCERR_MASK 0x0000000000000008UL
143 #define UVYH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000010UL
145 #define UVYH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000020UL
147 #define UVYH_EVENT_OCCURRED0_LH2_HCERR_MASK 0x0000000000000040UL
149 #define UVYH_EVENT_OCCURRED0_LH3_HCERR_MASK 0x0000000000000080UL
151 #define UVYH_EVENT_OCCURRED0_XB_HCERR_MASK 0x0000000000000100UL
153 #define UVYH_EVENT_OCCURRED0_RDM_HCERR_MASK 0x0000000000000200UL
155 #define UVYH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000400UL
157 #define UVYH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000800UL
159 #define UVYH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000001000UL
161 #define UVYH_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000002000UL
163 #define UVYH_EVENT_OCCURRED0_RH0_AOERR0_MASK 0x0000000000004000UL
165 #define UVYH_EVENT_OCCURRED0_RH1_AOERR0_MASK 0x0000000000008000UL
167 #define UVYH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000010000UL
169 #define UVYH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000020000UL
171 #define UVYH_EVENT_OCCURRED0_LH2_AOERR0_MASK 0x0000000000040000UL
173 #define UVYH_EVENT_OCCURRED0_LH3_AOERR0_MASK 0x0000000000080000UL
175 #define UVYH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000100000UL
177 #define UVYH_EVENT_OCCURRED0_RDM_AOERR0_MASK 0x0000000000200000UL
179 #define UVYH_EVENT_OCCURRED0_RT0_AOERR0_MASK 0x0000000000400000UL
181 #define UVYH_EVENT_OCCURRED0_RT1_AOERR0_MASK 0x0000000000800000UL
183 #define UVYH_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000001000000UL
185 #define UVYH_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000002000000UL
187 #define UVYH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000004000000UL
189 #define UVYH_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000008000000UL
191 #define UVYH_EVENT_OCCURRED0_RH0_AOERR1_MASK 0x0000000010000000UL
193 #define UVYH_EVENT_OCCURRED0_RH1_AOERR1_MASK 0x0000000020000000UL
195 #define UVYH_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000040000000UL
197 #define UVYH_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000080000000UL
199 #define UVYH_EVENT_OCCURRED0_LH2_AOERR1_MASK 0x0000000100000000UL
201 #define UVYH_EVENT_OCCURRED0_LH3_AOERR1_MASK 0x0000000200000000UL
203 #define UVYH_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000400000000UL
205 #define UVYH_EVENT_OCCURRED0_RDM_AOERR1_MASK 0x0000000800000000UL
207 #define UVYH_EVENT_OCCURRED0_RT0_AOERR1_MASK 0x0000001000000000UL
209 #define UVYH_EVENT_OCCURRED0_RT1_AOERR1_MASK 0x0000002000000000UL
211 #define UVYH_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000004000000000UL
213 #define UVYH_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000008000000000UL
215 #define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000010000000000UL
217 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000020000000000UL
219 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000040000000000UL
221 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000080000000000UL
223 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000100000000000UL
225 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000200000000000UL
227 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000400000000000UL
229 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000800000000000UL
231 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0001000000000000UL
233 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0002000000000000UL
235 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0004000000000000UL
237 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0008000000000000UL
239 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0010000000000000UL
241 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0020000000000000UL
243 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0040000000000000UL
245 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0080000000000000UL
247 #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0100000000000000UL
249 #define UVYH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0200000000000000UL
251 #define UVYH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0400000000000000UL
253 #define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0800000000000000UL
255 #define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x1000000000000000UL
257 #define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x2000000000000000UL
261 #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL
263 #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000000400UL
265 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK 0x0000000000020000UL
267 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK 0x0000000000040000UL
269 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK 0x0000000000080000UL
271 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK 0x0000000000100000UL
273 #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000200000UL
275 #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000400000UL
277 #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000800000UL
279 #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000001000000UL
281 #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000002000000UL
283 #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000004000000UL
285 #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000008000000UL
287 #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000010000000UL
289 #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000020000000UL
291 #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000040000000UL
293 #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK 0x0000000080000000UL
295 #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK 0x0000000100000000UL
297 #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK 0x0000000200000000UL
299 #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK 0x0000000400000000UL
301 #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000800000000UL
303 #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000001000000000UL
305 #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL
307 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000004000000000UL
309 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000008000000000UL
311 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000010000000000UL
313 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000020000000000UL
315 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000040000000000UL
317 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000080000000000UL
319 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000100000000000UL
321 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000200000000000UL
323 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000400000000000UL
325 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000800000000000UL
327 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0001000000000000UL
329 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0002000000000000UL
331 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0004000000000000UL
333 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0008000000000000UL
335 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0010000000000000UL
337 #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0020000000000000UL
339 #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0040000000000000UL
341 #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0080000000000000UL
343 #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0100000000000000UL
345 #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0200000000000000UL
347 #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL
349 #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK 0x0800000000000000UL
351 #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x1000000000000000UL
353 #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x2000000000000000UL
355 #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x4000000000000000UL
357 #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x8000000000000000UL
361 #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
363 #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
365 #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
367 #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
369 #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
371 #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
373 #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
375 #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
377 #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
379 #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
381 #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
383 #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
385 #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
387 #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
389 #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
391 #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
393 #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
395 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
397 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
399 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
401 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
403 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
405 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
407 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
409 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
411 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
413 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
415 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
417 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
419 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
421 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
423 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
425 #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
427 #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
429 #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
431 #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
433 #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
435 #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
437 #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
439 #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
441 #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
443 #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
445 #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
447 #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
451 #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
453 #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
455 #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
457 #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
459 #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
461 #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
463 #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
465 #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
467 #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
469 #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
471 #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
473 #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
475 #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
477 #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
479 #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
481 #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
483 #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
485 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
487 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
489 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
491 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
493 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
495 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
497 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
499 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
501 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
503 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
505 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
507 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
509 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
511 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
513 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
515 #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
517 #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
519 #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
521 #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
523 #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
525 #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
527 #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
529 #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
531 #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
533 #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
535 #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
537 #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
540 is_uv(UV4) ? 0x1000000000000000UL : \
541 is_uv(UV3) ? 0x0040000000000000UL : \
542 is_uv(UV2) ? 0x0040000000000000UL : \
543 0)
915 #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
921 #define UVH_EVENT_OCCURRED1 0x70080UL
926 #define UVYH_EVENT_OCCURRED1_IPI_INT_SHFT 0
927 #define UVYH_EVENT_OCCURRED1_IPI_INT_MASK 0x0000000000000001UL
929 #define UVYH_EVENT_OCCURRED1_EXTIO_INT0_MASK 0x0000000000000002UL
931 #define UVYH_EVENT_OCCURRED1_EXTIO_INT1_MASK 0x0000000000000004UL
933 #define UVYH_EVENT_OCCURRED1_EXTIO_INT2_MASK 0x0000000000000008UL
935 #define UVYH_EVENT_OCCURRED1_EXTIO_INT3_MASK 0x0000000000000010UL
937 #define UVYH_EVENT_OCCURRED1_PROFILE_INT_MASK 0x0000000000000020UL
939 #define UVYH_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000040UL
941 #define UVYH_EVENT_OCCURRED1_PROC_GENERAL_MASK 0x0000000000000080UL
943 #define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_MASK 0x0000000000000100UL
945 #define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_MASK 0x0000000000000200UL
947 #define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_MASK 0x0000000000000400UL
949 #define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_MASK 0x0000000000000800UL
951 #define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_MASK 0x0000000000001000UL
953 #define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_MASK 0x0000000000002000UL
955 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_MASK 0x0000000000004000UL
957 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_MASK 0x0000000000008000UL
959 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_MASK 0x0000000000010000UL
961 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_MASK 0x0000000000020000UL
963 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_MASK 0x0000000000040000UL
965 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_MASK 0x0000000000080000UL
967 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_MASK 0x0000000000100000UL
969 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_MASK 0x0000000000200000UL
971 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_MASK 0x0000000000400000UL
973 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_MASK 0x0000000000800000UL
975 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_MASK 0x0000000001000000UL
977 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_MASK 0x0000000002000000UL
979 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_MASK 0x0000000004000000UL
981 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_MASK 0x0000000008000000UL
983 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_MASK 0x0000000010000000UL
985 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_MASK 0x0000000020000000UL
987 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_MASK 0x0000000040000000UL
989 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_MASK 0x0000000080000000UL
991 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_MASK 0x0000000100000000UL
993 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_MASK 0x0000000200000000UL
995 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_MASK 0x0000000400000000UL
997 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_MASK 0x0000000800000000UL
999 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_MASK 0x0000001000000000UL
1001 #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_MASK 0x0000002000000000UL
1004 #define UV4H_EVENT_OCCURRED1_PROFILE_INT_SHFT 0
1005 #define UV4H_EVENT_OCCURRED1_PROFILE_INT_MASK 0x0000000000000001UL
1007 #define UV4H_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000002UL
1009 #define UV4H_EVENT_OCCURRED1_PROC_GENERAL_MASK 0x0000000000000004UL
1011 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK 0x0000000000000008UL
1013 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK 0x0000000000000010UL
1015 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK 0x0000000000000020UL
1017 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK 0x0000000000000040UL
1019 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK 0x0000000000000080UL
1021 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK 0x0000000000000100UL
1023 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK 0x0000000000000200UL
1025 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK 0x0000000000000400UL
1027 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK 0x0000000000000800UL
1029 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK 0x0000000000001000UL
1031 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK 0x0000000000002000UL
1033 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK 0x0000000000004000UL
1035 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK 0x0000000000008000UL
1037 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK 0x0000000000010000UL
1039 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK 0x0000000000020000UL
1041 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK 0x0000000000040000UL
1043 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_MASK 0x0000000000080000UL
1045 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_MASK 0x0000000000100000UL
1047 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_MASK 0x0000000000200000UL
1049 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_MASK 0x0000000000400000UL
1051 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_MASK 0x0000000000800000UL
1053 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_MASK 0x0000000001000000UL
1055 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_MASK 0x0000000002000000UL
1057 #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_MASK 0x0000000004000000UL
1059 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK 0x0000000008000000UL
1061 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK 0x0000000010000000UL
1063 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK 0x0000000020000000UL
1065 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK 0x0000000040000000UL
1067 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK 0x0000000080000000UL
1069 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK 0x0000000100000000UL
1071 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK 0x0000000200000000UL
1073 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK 0x0000000400000000UL
1075 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK 0x0000000800000000UL
1077 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK 0x0000001000000000UL
1079 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK 0x0000002000000000UL
1081 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK 0x0000004000000000UL
1083 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK 0x0000008000000000UL
1085 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK 0x0000010000000000UL
1087 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK 0x0000020000000000UL
1089 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK 0x0000040000000000UL
1091 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_MASK 0x0000080000000000UL
1093 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_MASK 0x0000100000000000UL
1095 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_MASK 0x0000200000000000UL
1097 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_MASK 0x0000400000000000UL
1099 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_MASK 0x0000800000000000UL
1101 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_MASK 0x0001000000000000UL
1103 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_MASK 0x0002000000000000UL
1105 #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_MASK 0x0004000000000000UL
1108 #define UV3H_EVENT_OCCURRED1_BAU_DATA_SHFT 0
1109 #define UV3H_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000001UL
1111 #define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK 0x0000000000000002UL
1113 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL
1115 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL
1117 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL
1119 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL
1121 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL
1123 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL
1125 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL
1127 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL
1129 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL
1131 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL
1133 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL
1135 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL
1137 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL
1139 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL
1141 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL
1143 #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL
1145 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK 0x0000000000040000UL
1147 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK 0x0000000000080000UL
1149 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK 0x0000000000100000UL
1151 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK 0x0000000000200000UL
1153 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK 0x0000000000400000UL
1155 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK 0x0000000000800000UL
1157 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK 0x0000000001000000UL
1159 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK 0x0000000002000000UL
1161 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK 0x0000000004000000UL
1163 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK 0x0000000008000000UL
1165 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK 0x0000000010000000UL
1167 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK 0x0000000020000000UL
1169 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK 0x0000000040000000UL
1171 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK 0x0000000080000000UL
1173 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK 0x0000000100000000UL
1175 #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK 0x0000000200000000UL
1177 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK 0x0000000400000000UL
1179 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK 0x0000000800000000UL
1181 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK 0x0000001000000000UL
1183 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK 0x0000002000000000UL
1185 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK 0x0000004000000000UL
1187 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK 0x0000008000000000UL
1189 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK 0x0000010000000000UL
1191 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK 0x0000020000000000UL
1193 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK 0x0000040000000000UL
1195 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK 0x0000080000000000UL
1197 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK 0x0000100000000000UL
1199 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK 0x0000200000000000UL
1201 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK 0x0000400000000000UL
1203 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK 0x0000800000000000UL
1205 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK 0x0001000000000000UL
1207 #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK 0x0002000000000000UL
1209 #define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK 0x0004000000000000UL
1211 #define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK 0x0008000000000000UL
1214 #define UV2H_EVENT_OCCURRED1_BAU_DATA_SHFT 0
1215 #define UV2H_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000001UL
1217 #define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK 0x0000000000000002UL
1219 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL
1221 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL
1223 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL
1225 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL
1227 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL
1229 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL
1231 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL
1233 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL
1235 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL
1237 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL
1239 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL
1241 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL
1243 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL
1245 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL
1247 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL
1249 #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL
1251 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK 0x0000000000040000UL
1253 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK 0x0000000000080000UL
1255 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK 0x0000000000100000UL
1257 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK 0x0000000000200000UL
1259 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK 0x0000000000400000UL
1261 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK 0x0000000000800000UL
1263 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK 0x0000000001000000UL
1265 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK 0x0000000002000000UL
1267 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK 0x0000000004000000UL
1269 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK 0x0000000008000000UL
1271 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK 0x0000000010000000UL
1273 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK 0x0000000020000000UL
1275 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK 0x0000000040000000UL
1277 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK 0x0000000080000000UL
1279 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK 0x0000000100000000UL
1281 #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK 0x0000000200000000UL
1283 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK 0x0000000400000000UL
1285 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK 0x0000000800000000UL
1287 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK 0x0000001000000000UL
1289 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK 0x0000002000000000UL
1291 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK 0x0000004000000000UL
1293 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK 0x0000008000000000UL
1295 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK 0x0000010000000000UL
1297 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK 0x0000020000000000UL
1299 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK 0x0000040000000000UL
1301 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK 0x0000080000000000UL
1303 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK 0x0000100000000000UL
1305 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK 0x0000200000000000UL
1307 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK 0x0000400000000000UL
1309 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK 0x0000800000000000UL
1311 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK 0x0001000000000000UL
1313 #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK 0x0002000000000000UL
1315 #define UV2H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK 0x0004000000000000UL
1317 #define UV2H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK 0x0008000000000000UL
1320 is_uv(UV5) ? 0x0000000000000002UL : \
1321 0)
1589 #define UVH_EVENT_OCCURRED1_ALIAS 0x70088UL
1595 #define UVH_EVENT_OCCURRED2 0x70100UL
1600 #define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 0
1601 #define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000000001UL
1603 #define UVYH_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000000002UL
1605 #define UVYH_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000004UL
1607 #define UVYH_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000008UL
1609 #define UVYH_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000010UL
1611 #define UVYH_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000020UL
1613 #define UVYH_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000040UL
1615 #define UVYH_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000080UL
1617 #define UVYH_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000100UL
1619 #define UVYH_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000200UL
1621 #define UVYH_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000400UL
1623 #define UVYH_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000800UL
1625 #define UVYH_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000001000UL
1627 #define UVYH_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000002000UL
1629 #define UVYH_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000004000UL
1631 #define UVYH_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000008000UL
1633 #define UVYH_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000010000UL
1635 #define UVYH_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000020000UL
1637 #define UVYH_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000040000UL
1639 #define UVYH_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000080000UL
1641 #define UVYH_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000100000UL
1643 #define UVYH_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000200000UL
1645 #define UVYH_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000400000UL
1647 #define UVYH_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000800000UL
1649 #define UVYH_EVENT_OCCURRED2_RTC_22_MASK 0x0000000001000000UL
1651 #define UVYH_EVENT_OCCURRED2_RTC_23_MASK 0x0000000002000000UL
1653 #define UVYH_EVENT_OCCURRED2_RTC_24_MASK 0x0000000004000000UL
1655 #define UVYH_EVENT_OCCURRED2_RTC_25_MASK 0x0000000008000000UL
1657 #define UVYH_EVENT_OCCURRED2_RTC_26_MASK 0x0000000010000000UL
1659 #define UVYH_EVENT_OCCURRED2_RTC_27_MASK 0x0000000020000000UL
1661 #define UVYH_EVENT_OCCURRED2_RTC_28_MASK 0x0000000040000000UL
1663 #define UVYH_EVENT_OCCURRED2_RTC_29_MASK 0x0000000080000000UL
1665 #define UVYH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000100000000UL
1667 #define UVYH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000200000000UL
1670 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0
1671 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL
1673 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL
1675 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL
1677 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL
1679 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL
1681 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL
1683 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL
1685 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL
1687 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL
1689 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL
1691 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL
1693 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL
1695 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL
1697 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL
1699 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL
1701 #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL
1703 #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000010000UL
1705 #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000020000UL
1707 #define UV4H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000040000UL
1709 #define UV4H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000080000UL
1711 #define UV4H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000100000UL
1713 #define UV4H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000200000UL
1715 #define UV4H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000400000UL
1717 #define UV4H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000800000UL
1719 #define UV4H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000001000000UL
1721 #define UV4H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000002000000UL
1723 #define UV4H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000004000000UL
1725 #define UV4H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000008000000UL
1727 #define UV4H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000010000000UL
1729 #define UV4H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000020000000UL
1731 #define UV4H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000040000000UL
1733 #define UV4H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000080000000UL
1735 #define UV4H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000100000000UL
1737 #define UV4H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000200000000UL
1739 #define UV4H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000400000000UL
1741 #define UV4H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000800000000UL
1743 #define UV4H_EVENT_OCCURRED2_RTC_18_MASK 0x0000001000000000UL
1745 #define UV4H_EVENT_OCCURRED2_RTC_19_MASK 0x0000002000000000UL
1747 #define UV4H_EVENT_OCCURRED2_RTC_20_MASK 0x0000004000000000UL
1749 #define UV4H_EVENT_OCCURRED2_RTC_21_MASK 0x0000008000000000UL
1751 #define UV4H_EVENT_OCCURRED2_RTC_22_MASK 0x0000010000000000UL
1753 #define UV4H_EVENT_OCCURRED2_RTC_23_MASK 0x0000020000000000UL
1755 #define UV4H_EVENT_OCCURRED2_RTC_24_MASK 0x0000040000000000UL
1757 #define UV4H_EVENT_OCCURRED2_RTC_25_MASK 0x0000080000000000UL
1759 #define UV4H_EVENT_OCCURRED2_RTC_26_MASK 0x0000100000000000UL
1761 #define UV4H_EVENT_OCCURRED2_RTC_27_MASK 0x0000200000000000UL
1763 #define UV4H_EVENT_OCCURRED2_RTC_28_MASK 0x0000400000000000UL
1765 #define UV4H_EVENT_OCCURRED2_RTC_29_MASK 0x0000800000000000UL
1767 #define UV4H_EVENT_OCCURRED2_RTC_30_MASK 0x0001000000000000UL
1769 #define UV4H_EVENT_OCCURRED2_RTC_31_MASK 0x0002000000000000UL
1772 #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0
1773 #define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
1775 #define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
1777 #define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
1779 #define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
1781 #define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
1783 #define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
1785 #define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
1787 #define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
1789 #define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
1791 #define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
1793 #define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
1795 #define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
1797 #define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
1799 #define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
1801 #define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
1803 #define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
1805 #define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
1807 #define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
1809 #define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
1811 #define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
1813 #define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
1815 #define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
1817 #define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
1819 #define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
1821 #define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
1823 #define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
1825 #define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
1827 #define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
1829 #define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
1831 #define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
1833 #define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
1835 #define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
1838 #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
1839 #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
1841 #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
1843 #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
1845 #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
1847 #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
1849 #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
1851 #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
1853 #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
1855 #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
1857 #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
1859 #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
1861 #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
1863 #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
1865 #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
1867 #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
1869 #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
1871 #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
1873 #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
1875 #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
1877 #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
1879 #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
1881 #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
1883 #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
1885 #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
1887 #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
1889 #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
1891 #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
1893 #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
1895 #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
1897 #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
1899 #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
1901 #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
1904 is_uv(UV5) ? 0x0000000000000008UL : \
1905 is_uv(UV4) ? 0x0000000000080000UL : \
1906 is_uv(UV3) ? 0x0000000000000002UL : \
1907 is_uv(UV2) ? 0x0000000000000002UL : \
1908 0)
2130 #define UVH_EVENT_OCCURRED2_ALIAS 0x70108UL
2136 #define UVH_EXTIO_INT0_BROADCAST 0x61448UL
2139 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0
2140 #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL
2181 is_uv(UV5) ? 0x600028UL : \
2182 is_uv(UV4) ? 0x600028UL : \
2183 is_uv(UV3) ? 0xc00028UL : \
2184 is_uv(UV2) ? 0xc00028UL : \
2185 0)
2191 #define UVYH_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL
2195 #define UV4H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL
2198 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT 0
2199 #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL
2201 #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL
2204 #define UV2H_GR0_GAM_GR_CONFIG_N_GR_SHFT 0
2205 #define UV2H_GR0_GAM_GR_CONFIG_N_GR_MASK 0x000000000000000fUL
2251 is_uv(UV4) ? 0x61b00UL : \
2252 is_uv(UV3) ? 0x61b00UL : \
2253 is_uv(UV2) ? 0x61b00UL : \
2258 #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
2259 #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
2261 #define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
2263 #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
2265 #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
2267 #define UVXH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
2269 #define UVXH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
2271 #define UVXH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
2273 #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
2354 is_uv(UV4) ? 0x61b40UL : \
2355 is_uv(UV3) ? 0x61b40UL : \
2356 is_uv(UV2) ? 0x61b40UL : \
2361 #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
2362 #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
2364 #define UVXH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
2366 #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
2368 #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
2370 #define UVXH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
2372 #define UVXH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
2374 #define UVXH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
2376 #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
2457 is_uv(UV4) ? 0x62100UL : \
2458 is_uv(UV3) ? 0x61f00UL : \
2459 is_uv(UV2) ? 0x61f00UL : \
2464 #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
2465 #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
2467 #define UVXH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
2469 #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
2471 #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
2473 #define UVXH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
2475 #define UVXH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
2477 #define UVXH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
2479 #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
2560 is_uv(UV4) ? 0x62140UL : \
2561 is_uv(UV3) ? 0x61f40UL : \
2562 is_uv(UV2) ? 0x61f40UL : \
2567 #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
2568 #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
2570 #define UVXH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
2572 #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
2574 #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
2576 #define UVXH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
2578 #define UVXH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
2580 #define UVXH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
2582 #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
2662 #define UVH_INT_CMPB 0x22080UL
2665 #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
2666 #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
2706 #define UVH_IPI_INT 0x60500UL
2709 #define UVH_IPI_INT_VECTOR_SHFT 0
2710 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
2712 #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
2714 #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
2716 #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
2718 #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
2783 #define UVH_NODE_ID 0x0UL
2786 #define UVH_NODE_ID_FORCE1_SHFT 0
2787 #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
2789 #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
2791 #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
2793 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
2798 #define UVXH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
2800 #define UVXH_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
2801 #define UVXH_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
2804 #define UVYH_NODE_ID_NODE_ID_MASK 0x0000007f00000000UL
2805 #define UVYH_NODE_ID_NI_PORT_MASK 0x7e00000000000000UL
2809 #define UV4H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL
2811 #define UV4H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL
2815 #define UV3H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL
2817 #define UV3H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL
2917 is_uv(UV5) ? 0x1400UL : \
2918 0)
2922 #define UVYH_NODE_PRESENT_0_NODES_SHFT 0
2923 #define UVYH_NODE_PRESENT_0_NODES_MASK 0xffffffffffffffffUL
2949 is_uv(UV5) ? 0x1408UL : \
2950 0)
2954 #define UVYH_NODE_PRESENT_1_NODES_SHFT 0
2955 #define UVYH_NODE_PRESENT_1_NODES_MASK 0xffffffffffffffffUL
2981 is_uv(UV4) ? 0x1400UL : \
2982 is_uv(UV3) ? 0x1400UL : \
2983 is_uv(UV2) ? 0x1400UL : \
2984 0)
2990 0)
2994 #define UVXH_NODE_PRESENT_TABLE_NODES_SHFT 0
2995 #define UVXH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
3031 is_uv(UV5) ? 0x470000UL : \
3032 0)
3037 #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_N_SKT_MASK 0x00000000000001c0UL
3039 #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_LS_ENABLE_MASK 0x0000000000001000UL
3041 #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_MK_TME_KEYID_BITS_MASK 0x00000000000f0000UL
3084 is_uv(UV5) ? 0x4700b0UL : \
3085 0)
3090 #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x000ffffffe000000UL
3092 #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK 0x0070000000000000UL
3094 #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
3097 is_uv(UV5) ? 0x000ffffffe000000UL : \
3098 0)
3138 is_uv(UV5) ? 0x473000UL : \
3139 0)
3144 #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x000ffffffc000000UL
3146 #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x03f0000000000000UL
3148 #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL
3151 is_uv(UV5) ? 0x000ffffffc000000UL : \
3152 0)
3195 is_uv(UV5) ? 0x474000UL : \
3196 0)
3201 #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x000ffffffc000000UL
3203 #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x03f0000000000000UL
3205 #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL
3208 is_uv(UV5) ? 0x000ffffffc000000UL : \
3209 0)
3252 is_uv(UV5) ? 0x473800UL : \
3253 0)
3257 0)
3261 #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0
3262 #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x000000000000007fUL
3291 is_uv(UV5) ? 0x474800UL : \
3292 0)
3296 0)
3300 #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0
3301 #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x000000000000007fUL
3330 is_uv(UV5) ? 0x470090UL : \
3331 0)
3336 #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_MASK 0x000ffffffe000000UL
3338 #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
3341 is_uv(UV5) ? 0x000ffffffe000000UL : \
3342 0)
3379 is_uv(UV4) ? 0x480000UL : \
3380 is_uv(UV3) ? 0x1600000UL : \
3381 is_uv(UV2) ? 0x1600000UL : \
3382 0)
3387 #define UVXH_RH_GAM_ADDR_MAP_CONFIG_N_SKT_MASK 0x00000000000003c0UL
3390 #define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT 0
3391 #define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
3394 #define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT 0
3395 #define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
3441 is_uv(UV4) ? 0x4800c8UL : \
3442 is_uv(UV3) ? 0x16000c8UL : \
3443 is_uv(UV2) ? 0x16000c8UL : \
3444 0)
3449 #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
3451 #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
3453 #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
3514 is_uv(UV4) ? 0x4800d0UL : \
3515 is_uv(UV3) ? 0x16000d0UL : \
3516 is_uv(UV2) ? 0x16000d0UL : \
3517 0)
3522 #define UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL
3568 is_uv(UV4) ? 0x4800d8UL : \
3569 is_uv(UV3) ? 0x16000d8UL : \
3570 is_uv(UV2) ? 0x16000d8UL : \
3571 0)
3576 #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
3578 #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
3580 #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
3641 is_uv(UV4) ? 0x4800e0UL : \
3642 is_uv(UV3) ? 0x16000e0UL : \
3643 is_uv(UV2) ? 0x16000e0UL : \
3644 0)
3649 #define UVXH_RH_GAM_ALIAS_1_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL
3695 is_uv(UV4) ? 0x4800e8UL : \
3696 is_uv(UV3) ? 0x16000e8UL : \
3697 is_uv(UV2) ? 0x16000e8UL : \
3698 0)
3703 #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
3705 #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
3707 #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
3768 is_uv(UV4) ? 0x4800f0UL : \
3769 is_uv(UV3) ? 0x16000f0UL : \
3770 is_uv(UV2) ? 0x16000f0UL : \
3771 0)
3776 #define UVXH_RH_GAM_ALIAS_2_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL
3822 is_uv(UV4) ? 0x480010UL : \
3823 is_uv(UV3) ? 0x1600010UL : \
3824 is_uv(UV2) ? 0x1600010UL : \
3825 0)
3830 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK 0x00f0000000000000UL
3832 #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
3836 #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x000ffffffc000000UL
3840 #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x00003ffffc000000UL
3844 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x00003ffff0000000UL
3846 #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MODE_MASK 0x4000000000000000UL
3850 #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x00003ffff0000000UL
3853 is_uv(UV4A) ? 0x000ffffffc000000UL : \
3854 is_uv(UV4) ? 0x00003ffffc000000UL : \
3855 is_uv(UV3) ? 0x00003ffff0000000UL : \
3856 is_uv(UV2) ? 0x00003ffff0000000UL : \
3857 0)
3932 is_uv(UV2) ? 0x1600030UL : \
3933 0)
3939 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_MASK 0x00003ffff8000000UL
3941 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_M_IO_MASK 0x000fc00000000000UL
3943 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_N_IO_MASK 0x00f0000000000000UL
3945 #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
3989 is_uv(UV4) ? 0x483000UL : \
3990 is_uv(UV3) ? 0x1603000UL : \
3991 0)
3995 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x000ffffffc000000UL
3997 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x03f0000000000000UL
3999 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL
4003 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x00003ffffc000000UL
4005 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x000fc00000000000UL
4007 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL
4011 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x00003ffffc000000UL
4013 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x000fc00000000000UL
4015 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL
4018 is_uv(UV4A) ? 0x000ffffffc000000UL : \
4019 is_uv(UV4) ? 0x00003ffffc000000UL : \
4020 is_uv(UV3) ? 0x00003ffffc000000UL : \
4021 0)
4085 is_uv(UV4) ? 0x484000UL : \
4086 is_uv(UV3) ? 0x1604000UL : \
4087 0)
4091 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x000ffffffc000000UL
4093 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x03f0000000000000UL
4095 #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL
4099 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x00003ffffc000000UL
4101 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x000fc00000000000UL
4103 #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL
4107 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x00003ffffc000000UL
4109 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x000fc00000000000UL
4111 #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL
4114 is_uv(UV4A) ? 0x000ffffffc000000UL : \
4115 is_uv(UV4) ? 0x00003ffffc000000UL : \
4116 is_uv(UV3) ? 0x00003ffffc000000UL : \
4117 0)
4181 is_uv(UV4) ? 0x483800UL : \
4182 is_uv(UV3) ? 0x1603800UL : \
4183 0)
4188 0)
4191 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0
4192 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x0000000000000fffUL
4195 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0
4196 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x0000000000007fffUL
4199 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0
4200 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x0000000000007fffUL
4207 0)
4247 is_uv(UV4) ? 0x484800UL : \
4248 is_uv(UV3) ? 0x1604800UL : \
4249 0)
4254 0)
4257 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0
4258 #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x0000000000000fffUL
4261 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0
4262 #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x0000000000007fffUL
4265 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0
4266 #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x0000000000007fffUL
4273 0)
4313 is_uv(UV4) ? 0x480028UL : \
4314 is_uv(UV3) ? 0x1600028UL : \
4315 is_uv(UV2) ? 0x1600028UL : \
4316 0)
4322 is_uv(UV4A) ? 0x000ffffffc000000UL : \
4323 is_uv(UV4) ? 0x00003ffffc000000UL : \
4324 is_uv(UV3) ? 0x00003ffffc000000UL : \
4325 is_uv(UV2) ? 0x00003ffffc000000UL : \
4326 0)
4328 #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
4332 #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x000ffffffc000000UL
4335 is_uv(UV4A) ? 0x000ffffffc000000UL : \
4336 is_uv(UV4) ? 0x00003ffffc000000UL : \
4337 is_uv(UV3) ? 0x00003ffffc000000UL : \
4338 is_uv(UV2) ? 0x00003ffffc000000UL : \
4339 0)
4395 is_uv(UV5) ? 0xe0000UL : \
4396 is_uv(UV4) ? 0xe0000UL : \
4397 is_uv(UV3) ? 0x340000UL : \
4398 is_uv(UV2) ? 0x340000UL : \
4399 0)
4402 #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
4403 #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
4443 #define UVH_RTC1_INT_CONFIG 0x615c0UL
4446 #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
4447 #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
4449 #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
4451 #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
4453 #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
4455 #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
4457 #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
4459 #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
4461 #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
4542 is_uv(UV5) ? 0xb0200UL : \
4543 is_uv(UV4) ? 0xb0200UL : \
4544 is_uv(UV3) ? 0x2d0200UL : \
4545 is_uv(UV2) ? 0x2d0200UL : \
4546 0)
4547 #define UV5H_SCRATCH5 0xb0200UL
4548 #define UV4H_SCRATCH5 0xb0200UL
4549 #define UV3H_SCRATCH5 0x2d0200UL
4550 #define UV2H_SCRATCH5 0x2d0200UL
4553 #define UVH_SCRATCH5_SCRATCH5_SHFT 0
4554 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4557 #define UVXH_SCRATCH5_SCRATCH5_SHFT 0
4558 #define UVXH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4561 #define UVYH_SCRATCH5_SCRATCH5_SHFT 0
4562 #define UVYH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4565 #define UV5H_SCRATCH5_SCRATCH5_SHFT 0
4566 #define UV5H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4569 #define UV4H_SCRATCH5_SCRATCH5_SHFT 0
4570 #define UV4H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4573 #define UV3H_SCRATCH5_SCRATCH5_SHFT 0
4574 #define UV3H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4577 #define UV2H_SCRATCH5_SCRATCH5_SHFT 0
4578 #define UV2H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4624 is_uv(UV5) ? 0xb0208UL : \
4625 is_uv(UV4) ? 0xb0208UL : \
4626 is_uv(UV3) ? 0x2d0208UL : \
4627 is_uv(UV2) ? 0x2d0208UL : \
4628 0)
4629 #define UV5H_SCRATCH5_ALIAS 0xb0208UL
4630 #define UV4H_SCRATCH5_ALIAS 0xb0208UL
4631 #define UV3H_SCRATCH5_ALIAS 0x2d0208UL
4632 #define UV2H_SCRATCH5_ALIAS 0x2d0208UL
4639 is_uv(UV5) ? 0xb0210UL : \
4640 is_uv(UV4) ? 0xb0210UL : \
4641 is_uv(UV3) ? 0x2d0210UL : \
4642 is_uv(UV2) ? 0x2d0210UL : \
4643 0)
4644 #define UV5H_SCRATCH5_ALIAS_2 0xb0210UL
4645 #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL
4646 #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL
4647 #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL