Lines Matching +full:0 +full:x8200
17 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
18 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
20 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
21 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
23 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
24 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
33 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
36 #define ARCH_PERFMON_EVENTSEL_UMASK2 (0xFFULL << 40)
38 #define INTEL_FIXED_BITS_MASK 0xFULL
40 #define INTEL_FIXED_0_KERNEL (1ULL << 0)
60 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
63 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
69 (0xFULL << AMD64_L3_SLICE_SHIFT)
71 (0x7ULL << AMD64_L3_SLICE_SHIFT)
75 (0xFFULL << AMD64_L3_THREAD_SHIFT)
77 (0x3ULL << AMD64_L3_THREAD_SHIFT)
84 (0x7ULL << AMD64_L3_COREID_SHIFT)
120 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_UMC GENMASK_ULL(7, 0)
130 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
131 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
132 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
139 #define PEBS_DATACFG_MEMINFO BIT_ULL(0)
190 #define ARCH_PERFMON_EXT_LEAF 0x00000023
191 #define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1
301 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
312 * The pseudo event-code for a fixed-mode PMC must be 0x00.
313 * The pseudo umask-code is 0xX. The X equals the index of the fixed
314 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
320 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
321 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
324 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
327 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
328 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
332 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
333 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
343 return !(code & 0xff); in use_fixed_pseudo_encoding()
362 #define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
371 #define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
379 * For the metric events, the pseudo event-code is 0x00.
381 * space, 0x80.
383 #define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
385 #define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
386 #define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
387 #define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
388 #define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
390 #define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */
391 #define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */
392 #define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */
393 #define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */
398 #define INTEL_TD_CFG_METRIC_CLEAR_BIT 0
412 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
441 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
444 #define INTEL_FIXED_VLBR_EVENT 0x1b00
488 #define EXT_PERFMON_DEBUG_FEATURES 0x80000022
494 #define IBS_CPUID_FEATURES 0x8000001b
498 * bit 0 is used to indicate the existence of IBS.
500 #define IBS_CAPS_AVAIL (1U<<0)
520 #define IBSCTL 0x1cc
522 #define IBSCTL_LVT_OFFSET_MASK 0x0F
529 #define IBS_FETCH_CNT 0xFFFF0000ULL
530 #define IBS_FETCH_MAX_CNT 0x0000FFFFULL
537 #define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
538 #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
543 #define IBS_OP_MAX_CNT 0x0000FFFFULL
544 #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
545 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */
552 static inline u32 get_ibs_caps(void) { return 0; } in get_ibs_caps()
561 * unused and ABI specified to be 0, so nobody should care what we do with
591 (regs)->sp = (unsigned long)__builtin_frame_address(0); \
593 regs->flags = 0; \
617 memset(cap, 0, sizeof(*cap)); in perf_get_x86_pmu_capability()
622 return 0; in perf_get_hw_event_config()
636 memset(lbr, 0, sizeof(*lbr)); in x86_perf_get_lbr()