Lines Matching +full:0 +full:x1901
10 #define MSR_EFER 0xc0000080 /* extended feature register */
11 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
12 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
13 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
14 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
15 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
16 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
17 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
18 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
21 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
44 #define X86_MEMTYPE_UC 0ull /* Uncacheable, a.k.a. Strong Uncacheable */
54 #define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */
55 #define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */
56 #define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */
57 #define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */
58 #define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */
59 #define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */
60 #define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */
61 #define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */
62 #define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */
63 #define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */
66 #define MSR_TEST_CTRL 0x00000033
70 #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
71 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
86 #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
87 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
90 #define MSR_PPIN_CTL 0x0000004e
91 #define MSR_PPIN 0x0000004f
93 #define MSR_IA32_PERFCTR0 0x000000c1
94 #define MSR_IA32_PERFCTR1 0x000000c2
95 #define MSR_FSB_FREQ 0x000000cd
96 #define MSR_PLATFORM_INFO 0x000000ce
100 #define MSR_IA32_UMWAIT_CONTROL 0xe1
101 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
105 * bit[1:0] zero.
107 #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
110 #define MSR_IA32_CORE_CAPS 0x000000cf
116 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
123 #define MSR_MTRRcap 0x000000fe
125 #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
126 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
213 #define MSR_IA32_FLUSH_CMD 0x0000010b
214 #define L1D_FLUSH BIT(0) /*
219 #define MSR_IA32_BBL_CR_CTL 0x00000119
220 #define MSR_IA32_BBL_CR_CTL3 0x0000011e
222 #define MSR_IA32_TSX_CTRL 0x00000122
223 #define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
226 #define MSR_IA32_MCU_OPT_CTRL 0x00000123
227 #define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
233 #define MSR_IA32_SYSENTER_CS 0x00000174
234 #define MSR_IA32_SYSENTER_ESP 0x00000175
235 #define MSR_IA32_SYSENTER_EIP 0x00000176
237 #define MSR_IA32_MCG_CAP 0x00000179
238 #define MSR_IA32_MCG_STATUS 0x0000017a
239 #define MSR_IA32_MCG_CTL 0x0000017b
240 #define MSR_ERROR_CONTROL 0x0000017f
241 #define MSR_IA32_MCG_EXT_CTL 0x000004d0
243 #define MSR_OFFCORE_RSP_0 0x000001a6
244 #define MSR_OFFCORE_RSP_1 0x000001a7
245 #define MSR_TURBO_RATIO_LIMIT 0x000001ad
246 #define MSR_TURBO_RATIO_LIMIT1 0x000001ae
247 #define MSR_TURBO_RATIO_LIMIT2 0x000001af
249 #define MSR_SNOOP_RSP_0 0x00001328
250 #define MSR_SNOOP_RSP_1 0x00001329
252 #define MSR_LBR_SELECT 0x000001c8
253 #define MSR_LBR_TOS 0x000001c9
255 #define MSR_IA32_POWER_CTL 0x000001fc
259 #define MSR_INTEGRITY_CAPS 0x000002d9
268 #define MSR_LBR_NHM_FROM 0x00000680
269 #define MSR_LBR_NHM_TO 0x000006c0
270 #define MSR_LBR_CORE_FROM 0x00000040
271 #define MSR_LBR_CORE_TO 0x00000060
273 #define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
278 #define LBR_INFO_CYCLES 0xffff
280 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
284 #define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)
285 #define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)
287 #define MSR_ARCH_LBR_CTL 0x000014ce
288 #define ARCH_LBR_CTL_LBREN BIT(0)
290 #define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
292 #define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
294 #define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
295 #define MSR_ARCH_LBR_DEPTH 0x000014cf
296 #define MSR_ARCH_LBR_FROM_0 0x00001500
297 #define MSR_ARCH_LBR_TO_0 0x00001600
298 #define MSR_ARCH_LBR_INFO_0 0x00001200
300 #define MSR_IA32_PEBS_ENABLE 0x000003f1
301 #define MSR_PEBS_DATA_CFG 0x000003f2
302 #define MSR_IA32_DS_AREA 0x00000600
303 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
307 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
310 #define PERF_CAP_PEBS_FORMAT 0xf00
315 #define MSR_IA32_RTIT_CTL 0x00000570
316 #define RTIT_CTL_TRACEEN BIT(0)
333 #define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
335 #define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
337 #define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
339 #define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
341 #define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
343 #define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
345 #define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
346 #define MSR_IA32_RTIT_STATUS 0x00000571
347 #define RTIT_STATUS_FILTEREN BIT(0)
354 #define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
355 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
356 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
357 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
358 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
359 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
360 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
361 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
362 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
363 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
364 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
365 #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
367 #define MSR_MTRRfix64K_00000 0x00000250
368 #define MSR_MTRRfix16K_80000 0x00000258
369 #define MSR_MTRRfix16K_A0000 0x00000259
370 #define MSR_MTRRfix4K_C0000 0x00000268
371 #define MSR_MTRRfix4K_C8000 0x00000269
372 #define MSR_MTRRfix4K_D0000 0x0000026a
373 #define MSR_MTRRfix4K_D8000 0x0000026b
374 #define MSR_MTRRfix4K_E0000 0x0000026c
375 #define MSR_MTRRfix4K_E8000 0x0000026d
376 #define MSR_MTRRfix4K_F0000 0x0000026e
377 #define MSR_MTRRfix4K_F8000 0x0000026f
378 #define MSR_MTRRdefType 0x000002ff
380 #define MSR_IA32_CR_PAT 0x00000277
388 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
389 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
390 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
391 #define MSR_IA32_LASTINTFROMIP 0x000001dd
392 #define MSR_IA32_LASTINTTOIP 0x000001de
394 #define MSR_IA32_PASID 0x00000d93
398 #define DEBUGCTLMSR_LBR_BIT 0 /* last branch recording */
413 #define MSR_PEBS_FRONTEND 0x000003f7
415 #define MSR_IA32_MC0_CTL 0x00000400
416 #define MSR_IA32_MC0_STATUS 0x00000401
417 #define MSR_IA32_MC0_ADDR 0x00000402
418 #define MSR_IA32_MC0_MISC 0x00000403
421 #define MSR_PKG_C3_RESIDENCY 0x000003f8
422 #define MSR_PKG_C6_RESIDENCY 0x000003f9
423 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
424 #define MSR_PKG_C7_RESIDENCY 0x000003fa
425 #define MSR_CORE_C3_RESIDENCY 0x000003fc
426 #define MSR_CORE_C6_RESIDENCY 0x000003fd
427 #define MSR_CORE_C7_RESIDENCY 0x000003fe
428 #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
429 #define MSR_PKG_C2_RESIDENCY 0x0000060d
430 #define MSR_PKG_C8_RESIDENCY 0x00000630
431 #define MSR_PKG_C9_RESIDENCY 0x00000631
432 #define MSR_PKG_C10_RESIDENCY 0x00000632
435 #define MSR_PKGC3_IRTL 0x0000060a
436 #define MSR_PKGC6_IRTL 0x0000060b
437 #define MSR_PKGC7_IRTL 0x0000060c
438 #define MSR_PKGC8_IRTL 0x00000633
439 #define MSR_PKGC9_IRTL 0x00000634
440 #define MSR_PKGC10_IRTL 0x00000635
444 #define MSR_VR_CURRENT_CONFIG 0x00000601
445 #define MSR_RAPL_POWER_UNIT 0x00000606
447 #define MSR_PKG_POWER_LIMIT 0x00000610
448 #define MSR_PKG_ENERGY_STATUS 0x00000611
449 #define MSR_PKG_PERF_STATUS 0x00000613
450 #define MSR_PKG_POWER_INFO 0x00000614
452 #define MSR_DRAM_POWER_LIMIT 0x00000618
453 #define MSR_DRAM_ENERGY_STATUS 0x00000619
454 #define MSR_DRAM_PERF_STATUS 0x0000061b
455 #define MSR_DRAM_POWER_INFO 0x0000061c
457 #define MSR_PP0_POWER_LIMIT 0x00000638
458 #define MSR_PP0_ENERGY_STATUS 0x00000639
459 #define MSR_PP0_POLICY 0x0000063a
460 #define MSR_PP0_PERF_STATUS 0x0000063b
462 #define MSR_PP1_POWER_LIMIT 0x00000640
463 #define MSR_PP1_ENERGY_STATUS 0x00000641
464 #define MSR_PP1_POLICY 0x00000642
466 #define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
467 #define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
468 #define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
471 #define MSR_CONFIG_TDP_NOMINAL 0x00000648
472 #define MSR_CONFIG_TDP_LEVEL_1 0x00000649
473 #define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
474 #define MSR_CONFIG_TDP_CONTROL 0x0000064B
475 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
477 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
478 #define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650
480 #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
481 #define MSR_PKG_ANY_CORE_C0_RES 0x00000659
482 #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
483 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
485 #define MSR_CORE_C1_RES 0x00000660
486 #define MSR_MODULE_C6_RES_MS 0x00000664
488 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
489 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
491 #define MSR_ATOM_CORE_RATIOS 0x0000066a
492 #define MSR_ATOM_CORE_VIDS 0x0000066b
493 #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
494 #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
496 #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
497 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
498 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
501 #define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
502 #define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
503 #define CET_SHSTK_EN BIT_ULL(0)
513 #define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
514 #define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
515 #define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
516 #define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
517 #define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
520 #define MSR_PPERF 0x0000064e
521 #define MSR_PERF_LIMIT_REASONS 0x0000064f
522 #define MSR_PM_ENABLE 0x00000770
523 #define MSR_HWP_CAPABILITIES 0x00000771
524 #define MSR_HWP_REQUEST_PKG 0x00000772
525 #define MSR_HWP_INTERRUPT 0x00000773
526 #define MSR_HWP_REQUEST 0x00000774
527 #define MSR_HWP_STATUS 0x00000777
537 #define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
538 #define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
539 #define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
540 #define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
543 #define HWP_MIN_PERF(x) (x & 0xff)
544 #define HWP_MAX_PERF(x) ((x & 0xff) << 8)
545 #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
546 #define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
547 #define HWP_EPP_PERFORMANCE 0x00
548 #define HWP_EPP_BALANCE_PERFORMANCE 0x80
549 #define HWP_EPP_BALANCE_POWERSAVE 0xC0
550 #define HWP_EPP_POWERSAVE 0xFF
551 #define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
552 #define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
555 #define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
556 #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
559 #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
560 #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
562 #define MSR_AMD64_MC0_MASK 0xc0010044
572 #define MSR_IA32_MC0_CTL2 0x00000280
575 #define MSR_P6_PERFCTR0 0x000000c1
576 #define MSR_P6_PERFCTR1 0x000000c2
577 #define MSR_P6_EVNTSEL0 0x00000186
578 #define MSR_P6_EVNTSEL1 0x00000187
580 #define MSR_KNC_PERFCTR0 0x00000020
581 #define MSR_KNC_PERFCTR1 0x00000021
582 #define MSR_KNC_EVNTSEL0 0x00000028
583 #define MSR_KNC_EVNTSEL1 0x00000029
586 #define MSR_IA32_PMC0 0x000004c1
589 #define MSR_RELOAD_PMC0 0x000014c1
590 #define MSR_RELOAD_FIXED_CTR0 0x00001309
593 #define MSR_IA32_PMC_V6_GP0_CTR 0x1900
594 #define MSR_IA32_PMC_V6_GP0_CFG_A 0x1901
595 #define MSR_IA32_PMC_V6_FX0_CTR 0x1980
599 #define MSR_IA32_MKTME_KEYID_PARTITIONING 0x00000087
605 #define MSR_AMD64_PATCH_LEVEL 0x0000008b
606 #define MSR_AMD64_TSC_RATIO 0xc0000104
607 #define MSR_AMD64_NB_CFG 0xc001001f
608 #define MSR_AMD64_PATCH_LOADER 0xc0010020
609 #define MSR_AMD_PERF_CTL 0xc0010062
610 #define MSR_AMD_PERF_STATUS 0xc0010063
611 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
612 #define MSR_AMD64_GUEST_TSC_FREQ 0xc0010134
613 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
614 #define MSR_AMD64_OSVW_STATUS 0xc0010141
615 #define MSR_AMD_PPIN_CTL 0xc00102f0
616 #define MSR_AMD_PPIN 0xc00102f1
617 #define MSR_AMD64_CPUID_FN_1 0xc0011004
618 #define MSR_AMD64_LS_CFG 0xc0011020
619 #define MSR_AMD64_DC_CFG 0xc0011022
620 #define MSR_AMD64_TW_CFG 0xc0011023
622 #define MSR_AMD64_DE_CFG 0xc0011029
627 #define MSR_AMD64_BU_CFG2 0xc001102a
628 #define MSR_AMD64_IBSFETCHCTL 0xc0011030
629 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031
630 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
633 #define MSR_AMD64_IBSOPCTL 0xc0011033
634 #define MSR_AMD64_IBSOPRIP 0xc0011034
635 #define MSR_AMD64_IBSOPDATA 0xc0011035
636 #define MSR_AMD64_IBSOPDATA2 0xc0011036
637 #define MSR_AMD64_IBSOPDATA3 0xc0011037
638 #define MSR_AMD64_IBSDCLINAD 0xc0011038
639 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039
642 #define MSR_AMD64_IBSCTL 0xc001103a
643 #define MSR_AMD64_IBSBRTARGET 0xc001103b
644 #define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
645 #define MSR_AMD64_IBSOPDATA4 0xc001103d
647 #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
648 #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
649 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
650 #define MSR_AMD64_SEV_ES_GHCB 0xc0010130
651 #define MSR_AMD64_SEV 0xc0010131
652 #define MSR_AMD64_SEV_ENABLED_BIT 0
688 #define MSR_AMD64_RMP_BASE 0xc0010132
689 #define MSR_AMD64_RMP_END 0xc0010133
690 #define MSR_AMD64_RMP_CFG 0xc0010136
691 #define MSR_AMD64_SEG_RMP_ENABLED_BIT 0
695 #define MSR_SVSM_CAA 0xc001f000
698 #define MSR_AMD_CPPC_CAP1 0xc00102b0
699 #define MSR_AMD_CPPC_ENABLE 0xc00102b1
700 #define MSR_AMD_CPPC_CAP2 0xc00102b2
701 #define MSR_AMD_CPPC_REQ 0xc00102b3
702 #define MSR_AMD_CPPC_STATUS 0xc00102b4
704 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
705 #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
706 #define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
707 #define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
709 #define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
710 #define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
711 #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
712 #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
715 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
716 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
717 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
720 #define MSR_AMD64_LBR_SELECT 0xc000010e
723 #define MSR_ZEN4_BP_CFG 0xc001102e
727 #define MSR_F19H_UMC_PERF_CTL 0xc0010800
728 #define MSR_F19H_UMC_PERF_CTR 0xc0010801
731 #define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
735 #define MSR_F17H_IRPERF 0xc00000e9
738 #define MSR_F16H_L2I_PERF_CTL 0xc0010230
739 #define MSR_F16H_L2I_PERF_CTR 0xc0010231
740 #define MSR_F16H_DR1_ADDR_MASK 0xc0011019
741 #define MSR_F16H_DR2_ADDR_MASK 0xc001101a
742 #define MSR_F16H_DR3_ADDR_MASK 0xc001101b
743 #define MSR_F16H_DR0_ADDR_MASK 0xc0011027
746 #define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
747 #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
748 #define MSR_F15H_PERF_CTL 0xc0010200
756 #define MSR_F15H_PERF_CTR 0xc0010201
764 #define MSR_F15H_NB_PERF_CTL 0xc0010240
765 #define MSR_F15H_NB_PERF_CTR 0xc0010241
766 #define MSR_F15H_PTSC 0xc0010280
767 #define MSR_F15H_IC_CFG 0xc0011021
768 #define MSR_F15H_EX_CFG 0xc001102c
771 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
772 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
773 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
775 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
777 #define MSR_FAM10H_NODE_ID 0xc001100c
780 #define MSR_K8_TOP_MEM1 0xc001001a
781 #define MSR_K8_TOP_MEM2 0xc001001d
782 #define MSR_AMD64_SYSCFG 0xc0010010
792 #define MSR_K8_INT_PENDING_MSG 0xc0010055
794 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000
795 #define MSR_K8_TSEG_ADDR 0xc0010112
796 #define MSR_K8_TSEG_MASK 0xc0010113
797 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
798 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
799 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
802 #define MSR_K7_EVNTSEL0 0xc0010000
803 #define MSR_K7_PERFCTR0 0xc0010004
804 #define MSR_K7_EVNTSEL1 0xc0010001
805 #define MSR_K7_PERFCTR1 0xc0010005
806 #define MSR_K7_EVNTSEL2 0xc0010002
807 #define MSR_K7_PERFCTR2 0xc0010006
808 #define MSR_K7_EVNTSEL3 0xc0010003
809 #define MSR_K7_PERFCTR3 0xc0010007
810 #define MSR_K7_CLK_CTL 0xc001001b
811 #define MSR_K7_HWCR 0xc0010015
812 #define MSR_K7_HWCR_SMMLOCK_BIT 0
816 #define MSR_K7_FID_VID_CTL 0xc0010041
817 #define MSR_K7_FID_VID_STATUS 0xc0010042
822 #define MSR_K6_WHCR 0xc0000082
823 #define MSR_K6_UWCCR 0xc0000085
824 #define MSR_K6_EPMR 0xc0000086
825 #define MSR_K6_PSOR 0xc0000087
826 #define MSR_K6_PFIR 0xc0000088
829 #define MSR_IDT_FCR1 0x00000107
830 #define MSR_IDT_FCR2 0x00000108
831 #define MSR_IDT_FCR3 0x00000109
832 #define MSR_IDT_FCR4 0x0000010a
834 #define MSR_IDT_MCR0 0x00000110
835 #define MSR_IDT_MCR1 0x00000111
836 #define MSR_IDT_MCR2 0x00000112
837 #define MSR_IDT_MCR3 0x00000113
838 #define MSR_IDT_MCR4 0x00000114
839 #define MSR_IDT_MCR5 0x00000115
840 #define MSR_IDT_MCR6 0x00000116
841 #define MSR_IDT_MCR7 0x00000117
842 #define MSR_IDT_MCR_CTRL 0x00000120
845 #define MSR_VIA_FCR 0x00001107
846 #define MSR_VIA_LONGHAUL 0x0000110a
847 #define MSR_VIA_RNG 0x0000110b
848 #define MSR_VIA_BCR2 0x00001147
851 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
852 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
853 #define MSR_TMTA_LRTI_READOUT 0x80868018
854 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
857 #define MSR_IA32_P5_MC_ADDR 0x00000000
858 #define MSR_IA32_P5_MC_TYPE 0x00000001
859 #define MSR_IA32_TSC 0x00000010
860 #define MSR_IA32_PLATFORM_ID 0x00000017
861 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
862 #define MSR_EBC_FREQUENCY_ID 0x0000002c
863 #define MSR_SMI_COUNT 0x00000034
866 #define MSR_IA32_FEAT_CTL 0x0000003a
867 #define FEAT_CTL_LOCKED BIT(0)
874 #define MSR_IA32_TSC_ADJUST 0x0000003b
875 #define MSR_IA32_BNDCFGS 0x00000d90
877 #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
879 #define MSR_IA32_XFD 0x000001c4
880 #define MSR_IA32_XFD_ERR 0x000001c5
881 #define MSR_IA32_XSS 0x00000da0
883 #define MSR_IA32_APICBASE 0x0000001b
886 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
888 #define MSR_IA32_UCODE_WRITE 0x00000079
889 #define MSR_IA32_UCODE_REV 0x0000008b
892 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
893 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
894 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
895 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
897 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
898 #define MSR_IA32_SMBASE 0x0000009e
900 #define MSR_IA32_PERF_STATUS 0x00000198
901 #define MSR_IA32_PERF_CTL 0x00000199
902 #define INTEL_PERF_CTL_MASK 0xffff
905 #define MSR_AMD_DBG_EXTN_CFG 0xc000010f
906 #define MSR_AMD_SAMP_BR_FROM 0xc0010300
910 #define MSR_IA32_MPERF 0x000000e7
911 #define MSR_IA32_APERF 0x000000e8
913 #define MSR_IA32_THERM_CONTROL 0x0000019a
914 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
916 #define THERM_INT_HIGH_ENABLE (1 << 0)
920 #define MSR_IA32_THERM_STATUS 0x0000019c
922 #define THERM_STATUS_PROCHOT (1 << 0)
925 #define MSR_THERM2_CTL 0x0000019d
929 #define MSR_IA32_MISC_ENABLE 0x000001a0
931 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
933 #define MSR_MISC_FEATURE_CONTROL 0x000001a4
934 #define MSR_MISC_PWR_MGMT 0x000001aa
936 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
937 #define ENERGY_PERF_BIAS_PERFORMANCE 0
944 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
946 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
950 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
952 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
960 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
963 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
970 #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
1024 #define MSR_MISC_FEATURES_ENABLES 0x00000140
1026 #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
1030 #define MSR_IA32_TSC_DEADLINE 0x000006E0
1033 #define MSR_TSX_FORCE_ABORT 0x0000010F
1035 #define MSR_TFA_RTM_FORCE_ABORT_BIT 0
1043 #define MSR_IA32_MCG_EAX 0x00000180
1044 #define MSR_IA32_MCG_EBX 0x00000181
1045 #define MSR_IA32_MCG_ECX 0x00000182
1046 #define MSR_IA32_MCG_EDX 0x00000183
1047 #define MSR_IA32_MCG_ESI 0x00000184
1048 #define MSR_IA32_MCG_EDI 0x00000185
1049 #define MSR_IA32_MCG_EBP 0x00000186
1050 #define MSR_IA32_MCG_ESP 0x00000187
1051 #define MSR_IA32_MCG_EFLAGS 0x00000188
1052 #define MSR_IA32_MCG_EIP 0x00000189
1053 #define MSR_IA32_MCG_RESERVED 0x0000018a
1056 #define MSR_P4_BPU_PERFCTR0 0x00000300
1057 #define MSR_P4_BPU_PERFCTR1 0x00000301
1058 #define MSR_P4_BPU_PERFCTR2 0x00000302
1059 #define MSR_P4_BPU_PERFCTR3 0x00000303
1060 #define MSR_P4_MS_PERFCTR0 0x00000304
1061 #define MSR_P4_MS_PERFCTR1 0x00000305
1062 #define MSR_P4_MS_PERFCTR2 0x00000306
1063 #define MSR_P4_MS_PERFCTR3 0x00000307
1064 #define MSR_P4_FLAME_PERFCTR0 0x00000308
1065 #define MSR_P4_FLAME_PERFCTR1 0x00000309
1066 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
1067 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
1068 #define MSR_P4_IQ_PERFCTR0 0x0000030c
1069 #define MSR_P4_IQ_PERFCTR1 0x0000030d
1070 #define MSR_P4_IQ_PERFCTR2 0x0000030e
1071 #define MSR_P4_IQ_PERFCTR3 0x0000030f
1072 #define MSR_P4_IQ_PERFCTR4 0x00000310
1073 #define MSR_P4_IQ_PERFCTR5 0x00000311
1074 #define MSR_P4_BPU_CCCR0 0x00000360
1075 #define MSR_P4_BPU_CCCR1 0x00000361
1076 #define MSR_P4_BPU_CCCR2 0x00000362
1077 #define MSR_P4_BPU_CCCR3 0x00000363
1078 #define MSR_P4_MS_CCCR0 0x00000364
1079 #define MSR_P4_MS_CCCR1 0x00000365
1080 #define MSR_P4_MS_CCCR2 0x00000366
1081 #define MSR_P4_MS_CCCR3 0x00000367
1082 #define MSR_P4_FLAME_CCCR0 0x00000368
1083 #define MSR_P4_FLAME_CCCR1 0x00000369
1084 #define MSR_P4_FLAME_CCCR2 0x0000036a
1085 #define MSR_P4_FLAME_CCCR3 0x0000036b
1086 #define MSR_P4_IQ_CCCR0 0x0000036c
1087 #define MSR_P4_IQ_CCCR1 0x0000036d
1088 #define MSR_P4_IQ_CCCR2 0x0000036e
1089 #define MSR_P4_IQ_CCCR3 0x0000036f
1090 #define MSR_P4_IQ_CCCR4 0x00000370
1091 #define MSR_P4_IQ_CCCR5 0x00000371
1092 #define MSR_P4_ALF_ESCR0 0x000003ca
1093 #define MSR_P4_ALF_ESCR1 0x000003cb
1094 #define MSR_P4_BPU_ESCR0 0x000003b2
1095 #define MSR_P4_BPU_ESCR1 0x000003b3
1096 #define MSR_P4_BSU_ESCR0 0x000003a0
1097 #define MSR_P4_BSU_ESCR1 0x000003a1
1098 #define MSR_P4_CRU_ESCR0 0x000003b8
1099 #define MSR_P4_CRU_ESCR1 0x000003b9
1100 #define MSR_P4_CRU_ESCR2 0x000003cc
1101 #define MSR_P4_CRU_ESCR3 0x000003cd
1102 #define MSR_P4_CRU_ESCR4 0x000003e0
1103 #define MSR_P4_CRU_ESCR5 0x000003e1
1104 #define MSR_P4_DAC_ESCR0 0x000003a8
1105 #define MSR_P4_DAC_ESCR1 0x000003a9
1106 #define MSR_P4_FIRM_ESCR0 0x000003a4
1107 #define MSR_P4_FIRM_ESCR1 0x000003a5
1108 #define MSR_P4_FLAME_ESCR0 0x000003a6
1109 #define MSR_P4_FLAME_ESCR1 0x000003a7
1110 #define MSR_P4_FSB_ESCR0 0x000003a2
1111 #define MSR_P4_FSB_ESCR1 0x000003a3
1112 #define MSR_P4_IQ_ESCR0 0x000003ba
1113 #define MSR_P4_IQ_ESCR1 0x000003bb
1114 #define MSR_P4_IS_ESCR0 0x000003b4
1115 #define MSR_P4_IS_ESCR1 0x000003b5
1116 #define MSR_P4_ITLB_ESCR0 0x000003b6
1117 #define MSR_P4_ITLB_ESCR1 0x000003b7
1118 #define MSR_P4_IX_ESCR0 0x000003c8
1119 #define MSR_P4_IX_ESCR1 0x000003c9
1120 #define MSR_P4_MOB_ESCR0 0x000003aa
1121 #define MSR_P4_MOB_ESCR1 0x000003ab
1122 #define MSR_P4_MS_ESCR0 0x000003c0
1123 #define MSR_P4_MS_ESCR1 0x000003c1
1124 #define MSR_P4_PMH_ESCR0 0x000003ac
1125 #define MSR_P4_PMH_ESCR1 0x000003ad
1126 #define MSR_P4_RAT_ESCR0 0x000003bc
1127 #define MSR_P4_RAT_ESCR1 0x000003bd
1128 #define MSR_P4_SAAT_ESCR0 0x000003ae
1129 #define MSR_P4_SAAT_ESCR1 0x000003af
1130 #define MSR_P4_SSU_ESCR0 0x000003be
1131 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
1133 #define MSR_P4_TBPU_ESCR0 0x000003c2
1134 #define MSR_P4_TBPU_ESCR1 0x000003c3
1135 #define MSR_P4_TC_ESCR0 0x000003c4
1136 #define MSR_P4_TC_ESCR1 0x000003c5
1137 #define MSR_P4_U2L_ESCR0 0x000003b0
1138 #define MSR_P4_U2L_ESCR1 0x000003b1
1140 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
1143 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
1144 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
1145 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
1146 #define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
1147 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
1148 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
1149 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
1150 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
1152 #define MSR_PERF_METRICS 0x00000329
1163 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
1166 #define MSR_IA32_VMX_BASIC 0x00000480
1167 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
1168 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
1169 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
1170 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
1171 #define MSR_IA32_VMX_MISC 0x00000485
1172 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
1173 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
1174 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
1175 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
1176 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
1177 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
1178 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
1179 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
1180 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
1181 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
1182 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
1183 #define MSR_IA32_VMX_VMFUNC 0x00000491
1184 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
1188 #define MSR_IA32_L3_QOS_CFG 0xc81
1189 #define MSR_IA32_L2_QOS_CFG 0xc82
1190 #define MSR_IA32_QM_EVTSEL 0xc8d
1191 #define MSR_IA32_QM_CTR 0xc8e
1192 #define MSR_IA32_PQR_ASSOC 0xc8f
1193 #define MSR_IA32_L3_CBM_BASE 0xc90
1194 #define MSR_RMID_SNC_CONFIG 0xca0
1195 #define MSR_IA32_L2_CBM_BASE 0xd10
1196 #define MSR_IA32_MBA_THRTL_BASE 0xd50
1199 #define MSR_IA32_MBA_BW_BASE 0xc0000200
1200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280
1201 #define MSR_IA32_EVT_CFG_BASE 0xc0000400
1204 #define MSR_VM_CR 0xc0010114
1205 #define MSR_VM_IGNNE 0xc0010115
1206 #define MSR_VM_HSAVE_PA 0xc0010117
1208 #define SVM_VM_CR_VALID_MASK 0x001fULL
1209 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
1210 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
1213 #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
1214 #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
1217 #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD
1218 #define LEGACY_XAPIC_DISABLED BIT(0) /*