Lines Matching +full:0 +full:x0000001
20 * array indices: 0,1 - HT threads, used with HT enabled cpu
51 P4_GEN_PEBS_BIND(1stl_cache_load_miss_retired, 0x0000001, 0x0000001),
52 P4_GEN_PEBS_BIND(2ndl_cache_load_miss_retired, 0x0000002, 0x0000001),
53 P4_GEN_PEBS_BIND(dtlb_load_miss_retired, 0x0000004, 0x0000001),
54 P4_GEN_PEBS_BIND(dtlb_store_miss_retired, 0x0000004, 0x0000002),
55 P4_GEN_PEBS_BIND(dtlb_all_miss_retired, 0x0000004, 0x0000003),
56 P4_GEN_PEBS_BIND(tagged_mispred_branch, 0x0018000, 0x0000010),
57 P4_GEN_PEBS_BIND(mob_load_replay_retired, 0x0000200, 0x0000001),
58 P4_GEN_PEBS_BIND(split_load_retired, 0x0000400, 0x0000001),
59 P4_GEN_PEBS_BIND(split_store_retired, 0x0000400, 0x0000002),
91 .cntr = { {0, -1, -1}, {2, -1, -1} },
100 .cntr = { {0, -1, -1}, {2, -1, -1} },
140 .cntr = { {0, -1, -1}, {2, -1, -1} },
149 .cntr = { {0, -1, -1}, {2, -1, -1} },
164 .cntr = { {0, -1, -1}, {2, -1, -1} },
181 .cntr = { {0, -1, -1}, {2, -1, -1} },
211 .cntr = { {0, -1, -1}, {2, -1, -1} },
230 .cntr = { {0, -1, -1}, {1, -1, -1} },
327 .cntr = { {0, -1, -1}, {2, -1, -1} },
384 .escr_emask = 0,
385 .cntr = { {0, -1, -1}, {2, -1, -1} },
390 .escr_emask = 0,
391 .cntr = { {0, -1, -1}, {2, -1, -1} },
396 .escr_emask = 0,
397 .cntr = { {0, -1, -1}, {2, -1, -1} },
402 .escr_emask = 0,
403 .cntr = { {0, -1, -1}, {2, -1, -1} },
521 [ C(RESULT_ACCESS) ] = 0x0,
528 [ C(RESULT_ACCESS) ] = 0x0,
535 [ C(RESULT_ACCESS) ] = 0x0,
540 [ C(RESULT_ACCESS) ] = 0x0,
631 return 0; in p4_get_alias_event()
635 for (i = 0; i < ARRAY_SIZE(p4_event_aliases); i++) { in p4_get_alias_event()
646 return 0; in p4_get_alias_event()
799 return 0; in p4_validate_raw_event()
805 int rc = 0; in p4_hw_config()
878 return 0; in p4_pmu_clear_cccr_ovf()
899 * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0); in p4_pmu_disable_pebs()
900 * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, 0); in p4_pmu_disable_pebs()
1038 int idx, handled = 0; in p4_pmu_handle_irq()
1068 perf_sample_data_init(&data, 0, hwc->last_period); in p4_pmu_handle_irq()
1075 x86_pmu_stop(event, 0); in p4_pmu_handle_irq()
1151 * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and
1152 * the metric between any ESCRs is laid in range [0xa0,0xe1]
1157 #define P4_ESCR_MSR_BASE 0x000003a0
1158 #define P4_ESCR_MSR_MAX 0x000003e1
1231 for (i = 0; i < P4_CNTR_LIMIT; i++) { in p4_next_cntr()
1255 for (i = 0, num = n; i < n; i++, num--) { in p4_pmu_schedule_events()
1259 pass = 0; in p4_pmu_schedule_events()
1321 return num ? -EINVAL : 0; in p4_pmu_schedule_events()
1324 PMU_FORMAT_ATTR(cccr, "config:0-31" );
1356 .cntr_mask64 = GENMASK_ULL(ARCH_P4_MAX_CCCR - 1, 0),
1400 wrmsrl_safe(reg, 0ULL); in p4_pmu_init()
1403 return 0; in p4_pmu_init()