Lines Matching +full:alternative +full:- +full:a
1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <asm/asm-offsets.h>
8 #include <asm/processor-flags.h>
9 #include <asm/ptrace-abi.h>
11 #include <asm/nospec-branch.h>
15 x86 function call convention, 64-bit:
16 -------------------------------------
17 arguments | callee-saved | extra caller-saved | return
18 [callee-clobbered] | | [callee-clobbered] |
19 ---------------------------------------------------------------------------
20 rdi rsi rdx rcx r8-9 | rbx rbp [*] r12-15 | r10-11 | rax, rdx [**]
23 functions when it sees tail-call optimization possibilities) rflags is
26 [*] In the frame-pointers case rbp is fixed to the stack frame.
28 [**] for struct return values wider than 64 bits the return convention is a
31 larger) the caller puts a pointer to an on-stack return struct
32 [allocated in the caller's stack frame] into the first argument - i.e.
36 For 32-bit we have the following conventions - kernel is built with
37 -mregparm=3 and -freg-struct-return:
39 x86 function calling convention, 32-bit:
40 ----------------------------------------
41 arguments | callee-saved | extra caller-saved | return
42 [callee-clobbered] | | [callee-clobbered] |
43 -------------------------------------------------------------------------
49 [*] In the frame-pointers case ebp is fixed to the stack frame.
51 [**] We build with -freg-struct-return, which on 32-bit means similar
52 semantics as on 64-bit: edx can be used for a second return value
53 (i.e. covering integer and structure sizes up to 64 bits) - after that
54 it gets more complex and more expensive: 3-word or larger struct returns
56 into regparm0, i.e. eax - the other arguments shift up and the
64 * 64-bit system call stack frame layout defines and helpers,
70 pushq %rsi /* pt_regs->si */
72 movq %rdi, 8(%rsp) /* pt_regs->di (overwriting original return address) */
73 /* We just clobbered the return address - use the IRET frame for unwinding: */
76 pushq %rdi /* pt_regs->di */
77 pushq %rsi /* pt_regs->si */
79 pushq \rdx /* pt_regs->dx */
80 pushq \rcx /* pt_regs->cx */
81 pushq \rax /* pt_regs->ax */
82 pushq %r8 /* pt_regs->r8 */
83 pushq %r9 /* pt_regs->r9 */
84 pushq %r10 /* pt_regs->r10 */
85 pushq %r11 /* pt_regs->r11 */
86 pushq %rbx /* pt_regs->rbx */
87 pushq %rbp /* pt_regs->rbp */
88 pushq %r12 /* pt_regs->r12 */
89 pushq %r13 /* pt_regs->r13 */
90 pushq %r14 /* pt_regs->r14 */
91 pushq %r15 /* pt_regs->r15 */
104 * Sanitize registers of values that a speculation attack might
106 * well before they could be put to use in a speculative execution
169 ALTERNATIVE "", "SET_NOFLUSH_BIT \reg", X86_FEATURE_PCID
175 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
188 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
191 * Test if the ASID needs a flush.
218 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
224 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
232 ALTERNATIVE "jmp .Ldone_\@", "", X86_FEATURE_PTI
249 /* Restore CR3 from a kernel context. May restore a user CR3 value. */
251 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
261 ALTERNATIVE "jmp .Lwrcr3_\@", "", X86_FEATURE_PCID
264 * Check if there's a pending flush for the user ASID we're
299 * instruction (NOTE! UNTRAIN_RET includes a RET instruction)
308 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
337 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_KERNEL_IBRS
358 * prevent a speculative swapgs when coming from kernel space.
360 * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
365 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
368 ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
399 * CPU/node NR is loaded from the limit (size) field of a special segment
408 * Fetch the per-CPU GSBASE value for this processor and put it in @reg.
409 * We normally use %gs for accessing per-CPU data, but we are setting up
410 * %gs here and obviously can not use %gs itself to access per-CPU data.
412 * Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and
414 * Thus the kernel would consume a guest's TSC_AUX if an NMI arrives