Lines Matching +full:smp +full:- +full:capable
1 # SPDX-License-Identifier: GPL-2.0
4 bool "64-bit kernel" if "$(ARCH)" = "x86"
7 Say yes to build a 64-bit kernel - formerly known as x86_64
8 Say no to build a 32-bit kernel - formerly known as i386
13 # Options that are inherently 32-bit kernel only:
27 # Options that are inherently 64-bit kernel only:
55 # ported to 32-bit as well. )
154 # Word-size accesses may read uninitialized data past the trailing \0
170 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
172 select GENERIC_IRQ_MIGRATION if SMP
176 select GENERIC_PENDING_IRQ if SMP
301 select HOTPLUG_PARALLEL if SMP && X86_64
302 select HOTPLUG_SMT if SMP
303 select HOTPLUG_SPLIT_STARTUP if SMP && X86_32
336 default "elf32-i386" if X86_32
337 default "elf64-x86-64" if X86_64
411 depends on X86_64 && SMP
431 …default $(success,$(srctree)/scripts/gcc-x86_64-has-stack-protector.sh $(CC) $(CLANG_FLAGS)) if 64…
432 default $(success,$(srctree)/scripts/gcc-x86_32-has-stack-protector.sh $(CC) $(CLANG_FLAGS))
436 the segment on 32-bit kernels.
440 config SMP config
441 bool "Symmetric multi-processing support"
447 If you say N here, the kernel will run on uni- and multiprocessor
462 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
463 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
474 This allows 32-bit apic IDs (so it can support very large systems),
485 bool "Enable MSI and MSI-x delivery by posted interrupts"
500 For old smp systems that do not have proper acpi support. Newer systems
534 bool "Support for big SMP systems with more than 8 CPUs"
535 depends on SMP && X86_32
540 bool "Support for extended (non-PC) x86 platforms"
548 for the following non-PC x86 platforms, depending on the value of
551 32-bit platforms (CONFIG_64BIT=n):
554 RDC R-321x SoC
556 STA2X11-based (e.g. Northville)
559 64-bit platforms (CONFIG_64BIT=y):
565 generic distribution kernel, say Y here - otherwise say N.
574 depends on SMP
578 Adds support for Numascale NumaChip large-SMP systems. Needed to
588 depends on SMP
591 supposed to run on these EM64T-based machines. Only choose this option
644 Select to build a kernel capable of supporting Intel MID (Mobile
702 - BayTrail
703 - Braswell
704 - Quark
722 bool "RDC R-321x SoC"
728 This option is needed for RDC R-321x system-on-chip, also known
729 as R-8610-(G).
733 bool "Support non-standard 32-bit SMP architectures"
734 depends on X86_32 && SMP
748 # On 32-bit this adds too big of NODES_SHIFT and we run out of page flags:
749 # On 32-bit SPARSEMEM adds too big of SECTIONS_WIDTH:
760 This adds support for boards based on the STA2X11 IO-Hub,
781 prompt "Single-depth WCHAN output"
794 Say Y here to enable options for running Linux under various hyper-
816 bool "paravirt-ops debugging"
824 depends on PARAVIRT && SMP
827 spinlock implementation with something virtualization-friendly
881 bool "Jailhouse non-root cell support"
885 This option allows to run Linux as guest in a Jailhouse non-root
895 a flexible, lightweight reference open-source hypervisor, built with
896 real-time and safety-criticality in mind. It is built for embedded
897 IOT with small footprint and real-time features. More details can be
901 bool "Intel TDX (Trust Domain Extensions) - Guest Support"
926 Use the IA-PC HPET (High Precision Event Timer) to manage
930 The HPET provides a stable time base on SMP
932 as it is off-chip. The interface used is documented
966 The GART supports full DMA access for devices with 32-bit access
975 32-bit limited device.
986 bool "Enable Maximum number of SMP Processors and NUMA Nodes"
987 depends on X86_64 && SMP && DEBUG_KERNEL
1000 # The ranges are different on 32-bit and 64-bit kernels, depending on
1010 default 1 if !SMP
1016 default 64 if SMP && X86_BIGSMP
1017 default 8 if SMP && !X86_BIGSMP
1018 default 1 if !SMP
1023 default 8192 if SMP && CPUMASK_OFFSTACK
1024 default 512 if SMP && !CPUMASK_OFFSTACK
1025 default 1 if !SMP
1031 default 8 if SMP
1032 default 1 if !SMP
1038 default 64 if SMP
1039 default 1 if !SMP
1042 int "Maximum number of CPUs" if SMP && !MAXSMP
1056 depends on SMP
1062 by sharing mid-level caches, last-level cache tags or internal
1066 def_bool y if SMP
1070 prompt "Multi-core scheduler support"
1071 depends on SMP
1073 Multi-core scheduler support improves the CPU scheduler's decision
1074 making when dealing with multi-core CPU chips at a cost of slightly
1101 depends on !SMP && X86_LOCAL_APIC
1106 depends on X86_32 && !SMP && !X86_32_NON_STANDARD
1109 integrated interrupt controller in the CPU. If you have a single-CPU
1113 all. The local APIC supports CPU-generated self-interrupts (timer,
1118 bool "IO-APIC support on uniprocessors"
1121 An IO-APIC (I/O Advanced Programmable Interrupt Controller) is an
1122 SMP-capable replacement for PC-style interrupt controllers. Most
1123 SMP systems and many recent uniprocessor systems have one.
1125 If you have a single-CPU system with an IO-APIC, you can say Y here
1127 an IO-APIC, then the kernel will still run with no slowdown at all.
1131 depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC || PCI_MSI
1138 depends on SMP
1155 entry in the chipset's IO-APIC is masked (as, e.g. the RT
1229 mode, which is an 80286-era approximation of 16-bit real mode.
1237 a 16-bit DOS program where 16-bit performance matters, vm86
1241 Note that any app that works on a 64-bit kernel is unlikely to
1242 need this option, as 64-bit kernels don't, and can't, support
1243 V8086 mode. This option is also unrelated to 16-bit protected
1244 mode and is not needed to run most 16-bit programs under Wine.
1256 bool "Enable support for 16-bit segments" if EXPERT
1260 This option is required by programs like Wine to run 16-bit
1263 plus 16K runtime memory on x86-64,
1336 CS5530A and CS5536 chipsets and the RDC R-321x SoC.
1354 depends on MICROCODE && SMP
1384 tristate "/dev/cpu/*/msr - Model-specific register support"
1387 Model-Specific Registers (MSRs). It is a character device with
1389 MSR accesses are directed to a specific CPU on multi-processor
1393 tristate "/dev/cpu/*/cpuid - CPU information support"
1409 However, the address space of 32-bit x86 processors is only 4
1428 PAE implements 3-level paging on IA32 processors. PAE is fully
1444 Select this if you have a 32-bit processor and between 1 and 4
1452 Select this if you have a 32-bit processor and more than 4
1471 will also likely make your kernel incompatible with binary-only
1511 larger swapspace support for non-overcommit purposes. It
1516 bool "Enable 5-level page tables support"
1522 5-level paging enables access to larger address space:
1529 support 4- or 5-level paging.
1531 See Documentation/arch/x86/x86_64/5level-paging.rst for more
1577 depends on SMP
1583 Enable NUMA (Non-Uniform Memory Access) support.
1589 For 64-bit this is recommended if the system is Intel Core i7
1592 For 32-bit this is only needed if you boot a 32-bit
1593 kernel on a 64-bit NUMA platform.
1649 See Documentation/admin-guide/mm/memory-hotplug.rst for more information.
1665 tristate "Support non-standard NVDIMMs and ADR protected memory"
1672 Treat memory marked using the non-standard e820 type of 12 as used
1673 by the Intel Sandy Bridge-EP reference BIOS as protected memory.
1680 bool "Allocate 3rd-level pagetables from highmem"
1685 low memory. Setting this option will put user-space page table
1698 Documentation/admin-guide/kernel-parameters.rst to adjust this.
1706 BIOS-originated corruption always affects the same memory,
1740 emulation can be found in <file:arch/x86/math-emu/README>.
1752 a video (VGA) card on a PCI or AGP bus. Enabling write-combining
1766 The AMD K6-2 (stepping 8 and above) and K6-3 processors have two
1768 write-combining. All of these processors are supported by this code
1771 Saying Y here also fixes a problem with buggy SMP BIOSes which only
1795 int "MTRR cleanup enable value (0-1)"
1803 int "MTRR cleanup spare reg num (0-7)"
1823 spontaneous reboots) or a non-working video driver.
1839 specific cases in protected and virtual-8086 modes. Emulated
1846 # https://github.com/llvm/llvm-project/commit/e0b89df2e0f0130881bf6c39bf31d7f6aac00e0f
1847 # https://github.com/llvm/llvm-project/commit/dfcf69770bc522b9e411c66454934a37c1f35332
1848 def_bool ((CC_IS_GCC && $(cc-option, -fcf-protection=branch -mindirect-branch-register)) || \
1850 $(as-instr,endbr64)
1861 # https://github.com/llvm/llvm-project/commit/9d7001eba9c4cb311e03cd8cdc231f9e579f2d0f
1867 hardware support course-grain forward-edge Control Flow Integrity
1882 # Note: only available in 64-bit mode
1888 page-based protections, but without requiring modification of the
1891 For details, see Documentation/core-api/protection-keys.rst
1919 and =auto. See Documentation/admin-guide/kernel-parameters.txt for more
1929 TSX is disabled if possible - equals to tsx=off command line parameter.
1934 TSX is always enabled on TSX capable HW - equals the tsx=on command
1940 TSX is enabled on TSX capable HW that is believed to be safe against
1941 side channel attacks- equals the tsx=auto command line parameter.
2013 resultant kernel should continue to boot on existing non-EFI
2024 See Documentation/admin-guide/efi-stub.rst for more information.
2044 bool "EFI mixed-mode support"
2047 Enabling this feature allows a 64-bit kernel to be booted
2048 on a 32-bit firmware, provided that your CPU supports 64-bit
2051 Note that it is not possible to boot a mixed-mode enabled
2052 kernel via the EFI boot stub - a bootloader that supports
2061 Export EFI runtime memory regions to /sys/firmware/efi/runtime-map.
2065 See also Documentation/ABI/testing/sysfs-firmware-efi-runtime-map.
2134 command line boot parameter passed to the panic-ed
2135 kernel. Please take a look at Documentation/admin-guide/kdump/kdump.rst
2177 On 64-bit, the kernel physical and virtual addresses are
2184 On 32-bit, the kernel physical and virtual addresses are
2215 If bootloader loads the kernel at a non-aligned address and
2219 If bootloader loads the kernel at a non-aligned address and
2227 On 32-bit this value must be a multiple of 0x2000. On 64-bit
2277 to 64-bit linear addresses, allowing software to use of the
2285 depends on SMP
2289 prompt "Disable the 32-bit vDSO (needed for glibc 2.3.3)"
2293 presented with a 32-bit vDSO that is not mapped at the address
2303 dl_main: Assertion `(void *) ph->p_vaddr == _rtld_local._dl_sysinfo_dso' failed!
2306 option from 1 to 0, which turns off the 32-bit vDSO entirely.
2341 certain uses of the vsyscall area as an ASLR-bypassing
2356 bool "Built-in kernel command line"
2368 Systems with fully functional boot loaders (i.e. non-embedded)
2372 string "Built-in kernel command string"
2384 In most cases, the command line (whether built-in or provided
2389 bool "Built-in command line overrides boot loader arguments"
2393 command line, and use ONLY the built-in command line.
2402 Linux can allow user programs to install a per-process x86
2404 call. This is required to run 16-bit or segmented code such as
2409 context switches and increases the low-level kernel attack
2452 def_bool $(success,echo 'int __seg_fs fs; int __seg_gs gs;' | $(CC) -x c - -S -o /dev/null)
2456 # -fsanitize=kernel-address (KASAN) and -fsanitize=thread (KCSAN)
2471 def_bool $(cc-option,-mharden-sls=all)
2474 def_bool $(cc-option,-mfunction-return=thunk-extern)
2477 def_bool $(cc-option,-fpatchable-function-entry=16,16)
2487 # Basically: FUNCTION_ALIGNMENT - 5*CFI_CLANG
2549 kernel-to-user data leaks by avoiding speculative indirect
2550 branches. Requires a compiler with -mindirect-branch=thunk-extern
2554 bool "Enable return-thunks"
2559 Compile the kernel with the return-thunks compiler option to guard
2560 against kernel-to-user data leaks by avoiding return speculation.
2561 Requires a compiler with -mfunction-return=thunk-extern
2579 SKL Return-Stack-Buffer (RSB) underflow issue. The mitigation is off
2581 retbleed=stuff option. For non-affected systems the overhead of this
2582 option is marginal as the call depth tracking is using run-time
2597 kernel command line with 'debug-callthunks'.
2607 spec_rstack_overflow={ibpb,ibpb-vmexit} mitigations.
2623 Enable the SRSO mitigation needed on AMD Zen1-4 machines.
2626 bool "Mitigate Straight-Line-Speculation"
2631 Compile the kernel with straight-line-speculation options to guard
2654 See also <file:Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst>
2657 bool "Mitigate Spectre-BHB (Branch History Injection)"
2664 See <file:Documentation/admin-guide/hw-vuln/spectre.rst>
2674 See also <file:Documentation/admin-guide/hw-vuln/mds.rst>
2685 See also <file:Documentation/admin-guide/hw-vuln/tsx_async_abort.rst>
2693 Stale Data Vulnerabilities are a class of memory-mapped I/O (MMIO)
2697 <file:Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst>
2707 See <file:Documentation/admin-guide/hw-vuln/l1tf.rst
2730 See also <file:Documentation/admin-guide/hw-vuln/spectre.rst>
2742 See also <file:Documentation/admin-guide/hw-vuln/spectre.rst>
2756 <file:Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst>
2795 battery status information, and user-space programs will receive
2805 and more information, read <file:Documentation/power/apm-acpi.rst>
2806 and the Battery Powered Linux mini-HOWTO, available from
2811 VESA-compliant "green" monitors.
2863 feature is turned off -- see "Do CPU IDLE calls", below). This
2892 do with your VESA-compliant power-saving monitor. Further, this
2893 option doesn't work for all laptops -- it might not turn off your
2903 needs to. Unfortunately, some BIOSes do not -- especially those in
2927 PCI-based systems don't have any BIOS at all. Linux can also try to
2948 bool "OLPC XO-1"
2960 # x86-64 doesn't support PCI BIOS access from long mode so always go direct.
3002 architectures -- if your target machine is modern, it probably does
3007 # x86_64 have no ISA slots, but can have ISA-style DMA.
3009 bool "ISA-style DMA support" if (X86_64 && EXPERT)
3012 Enables ISA-style DMA support for devices requiring such controllers.
3031 PCI-IDs of several on-chip devices, so its a good dependency
3037 tristate "NatSemi SCx200 27MHz High-Resolution Timer Support"
3041 This driver provides a clocksource built upon the on-chip
3042 27MHz high-resolution timer. Its also a workaround for
3043 NSC Geode SC-1100's buggy TSC, which loses time when the
3060 bool "OLPC XO-1 Power Management"
3063 Add support for poweroff and suspend of the OLPC XO-1 laptop.
3066 bool "OLPC XO-1 Real Time Clock"
3069 Add support for the XO-1 real time clock, which can be used as a
3073 bool "OLPC XO-1 SCI extras"
3078 Add support for SCI-based features of the OLPC XO-1 laptop:
3079 - EC-driven system wakeups
3080 - Power button
3081 - Ebook switch
3082 - Lid switch
3083 - AC adapter status updates
3084 - Battery status updates
3087 bool "OLPC XO-1.5 SCI extras"
3091 Add support for SCI-based features of the OLPC XO-1.5 laptop:
3092 - EC-driven system wakeups
3093 - AC adapter status updates
3094 - Battery status updates
3130 bool "Technologic Systems TS-5500 platform support"
3136 This option enables system support for the Technologic Systems TS-5500.
3159 Include code to run legacy 32-bit programs under a
3160 64-bit kernel. You should likely turn this on, unless you're
3161 100% sure that you don't have any 32-bit programs left.
3168 Make IA32 emulation disabled by default. This prevents loading 32-bit
3169 processes and access to 32-bit syscalls. If unsure, leave it to its
3173 bool "x32 ABI for 64-bit mode"
3175 # llvm-objcopy does not convert x86_64 .note.gnu.property or
3179 depends on $(success,$(OBJCOPY) --version | head -n1 | grep -qv llvm)
3181 Include code to run binaries for the x32 native 32-bit ABI
3182 for 64-bit processors. An x32 process gets access to the
3183 full 64-bit register file and wide data path while leaving