Lines Matching +full:0 +full:x1c000
48 #define __SAVE __asm__ __volatile__("save %sp, -0x40, %sp\n\t")
54 int count = 0; in die_if_kernel()
82 !(((unsigned long) rw) & 0x7)) { in die_if_kernel()
95 if(type < 0x80) { in do_hw_interrupt()
105 (void __user *)regs->pc, type - 0x80); in do_hw_interrupt()
140 #if 0 in do_memaccess_unaligned()
146 /* FIXME: Should dig out mna address */ (void *)0, in do_memaccess_unaligned()
150 static unsigned long init_fsr = 0x0UL;
152 { ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
153 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
154 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL,
155 ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL, ~0UL };
172 fpsave(&fptask->thread.float_regs[0], &fptask->thread.fsr, in do_fpd_trap()
173 &fptask->thread.fpqueue[0], &fptask->thread.fpqdepth); in do_fpd_trap()
177 fpload(¤t->thread.float_regs[0], ¤t->thread.fsr); in do_fpd_trap()
180 fpload(&init_fregs[0], &init_fsr); in do_fpd_trap()
185 fpload(&init_fregs[0], &init_fsr); in do_fpd_trap()
188 fpload(¤t->thread.float_regs[0], ¤t->thread.fsr); in do_fpd_trap()
204 int ret = 0;
221 fpsave(&fake_regs[0], &fake_fsr, &fake_queue[0], &fake_depth);
225 fpsave(&fpt->thread.float_regs[0], &fpt->thread.fsr,
226 &fpt->thread.fpqueue[0], &fpt->thread.fpqdepth);
231 switch ((fpt->thread.fsr & 0x1c000)) {
256 fpload(¤t->thread.float_regs[0], ¤t->thread.fsr);
281 if ((fsr & 0x1c000) == (1 << 14)) {
282 if (fsr & 0x10)
284 else if (fsr & 0x08)
286 else if (fsr & 0x04)
288 else if (fsr & 0x02)
290 else if (fsr & 0x01)
298 if(calls > 0)
299 calls=0;