Lines Matching +full:0 +full:xfffffff0
25 #define SRMMU_ET_MASK 0x3
26 #define SRMMU_ET_INVALID 0x0
27 #define SRMMU_ET_PTD 0x1
28 #define SRMMU_ET_PTE 0x2
29 #define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
32 #define SRMMU_CTX_PMASK 0xfffffff0
33 #define SRMMU_PTD_PMASK 0xfffffff0
34 #define SRMMU_PTE_PMASK 0xffffff00
44 #define SRMMU_CACHE 0x80
45 #define SRMMU_DIRTY 0x40
46 #define SRMMU_REF 0x20
47 #define SRMMU_NOREAD 0x10
48 #define SRMMU_EXEC 0x08
49 #define SRMMU_WRITE 0x04
50 #define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
51 #define SRMMU_PRIV 0x1c
52 #define SRMMU_PRIV_RDONLY 0x18
54 #define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
57 #define SRMMU_SWP_TYPE_MASK 0x1f
59 #define SRMMU_SWP_OFF_MASK 0xfffff
80 /* SRMMU Register addresses in ASI 0x4. These are valid for all
83 #define SRMMU_CTRL_REG 0x00000000
84 #define SRMMU_CTXTBL_PTR 0x00000100
85 #define SRMMU_CTX_REG 0x00000200
86 #define SRMMU_FAULT_STATUS 0x00000300
87 #define SRMMU_FAULT_ADDR 0x00000400
90 mov 0, tmp1; \
122 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": : in srmmu_flush_whole_tlb()
123 "r" (0x400), /* Flush entire TLB!! */ in srmmu_flush_whole_tlb()
133 __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" : in srmmu_get_pte()
135 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE)); in srmmu_get_pte()