Lines Matching +full:system +full:- +full:clock +full:- +full:frequency
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
92 #define BBC_WDACTION_RST 0x01 /* When set, watchdog causes system reset.
105 * the entire system.
125 #define BBC_PSRC_SPGSYS 0x0010 /* System reset via BBC_SPG register */
126 #define BBC_PSRC_JTAG 0x0020 /* System reset via JTAG+ */
127 #define BBC_PSRC_BUTTON 0x0040 /* System reset via push-button dongle */
128 #define BBC_PSRC_PWRUP 0x0080 /* System reset via power-up */
136 #define BBC_PSRC_SYNTH 0x8000 /* System reset when on-board clock synthesizers
139 #define BBC_PSRC_WDT 0x10000 /* System reset via Super I/O watchdog */
140 #define BBC_PSRC_RSC 0x20000 /* System reset via RSC remote monitoring
158 /* Clock Synthesizers Control register. This register provides the big-bang
159 * programming interface to the two clock synthesizers of the machine.
165 #define BBC_CSC_RST 0x80 /* Generate system reset when S_LOAD==1 */
168 * clock frequency change trigger to the main system devices (Schizo and
172 * a) Choose new frequency: full, 1/2 or 1/32
173 * b) Program this desired frequency into the cpus and Schizo.
175 * d) 16 system clocks later, clear this register.
177 #define BBC_ES_CTRL_1_1 0x01 /* Full frequency */
178 #define BBC_ES_CTRL_1_2 0x02 /* 1/2 frequency */
179 #define BBC_ES_CTRL_1_32 0x20 /* 1/32 frequency */
183 * of BBC clock cycles (which is half the system frequency) between
190 * of BBC clock cycles (which is half the system frequency) between
197 * BBC clock cycles (which is half the system frequency) between the
198 * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
203 /* Energy Star Frequency Switch Latency register. This is the number of
204 * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
205 * edge of the Safari clock at the new frequency.
215 /* Keyboard Beep Counter register. There is a free-running counter inside
216 * the BBC which runs at half the system clock. The bit set in this register
219 * generator automatically selects a different bit to use if the system clock