Lines Matching +full:de +full:- +full:assert

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13  * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
28 #define BBC_ES_ACT	0x10	/* [W] E* Assert Change Time	*/
29 #define BBC_ES_DACT	0x14	/* [B] E* De-Assert Change Time	*/
30 #define BBC_ES_DABT	0x15	/* [B] E* De-Assert Bypass Time	*/
31 #define BBC_ES_ABT	0x16	/* [H] E* Assert Bypass Time	*/
38 #define BBC_I2C_0_S1	0x2e	/* [B] I2C ctrlr-0 reg S1	*/
39 #define BBC_I2C_0_S0	0x2f	/* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1	0x30	/* [B] I2C ctrlr-1 reg S1	*/
41 #define BBC_I2C_1_S0	0x31	/* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
100 #define BBC_SPG_CPU0	0x01 /* Assert POR for processor 0	*/
101 #define BBC_SPG_CPU1	0x02 /* Assert POR for processor 1	*/
102 #define BBC_SPG_CPU2	0x04 /* Assert POR for processor 2	*/
103 #define BBC_SPG_CPU3	0x08 /* Assert POR for processor 3	*/
112 #define BBC_SXG_CPU0	0x01 /* Assert XIR for processor 0	*/
113 #define BBC_SXG_CPU1	0x02 /* Assert XIR for processor 1	*/
114 #define BBC_SXG_CPU2	0x04 /* Assert XIR for processor 2	*/
115 #define BBC_SXG_CPU3	0x08 /* Assert XIR for processor 3	*/
127 #define BBC_PSRC_BUTTON	0x0040 /* System reset via push-button dongle	*/
128 #define BBC_PSRC_PWRUP	0x0080 /* System reset via power-up		*/
136 #define BBC_PSRC_SYNTH	0x8000 /* System reset when on-board clock synthesizers
158 /* Clock Synthesizers Control register.  This register provides the big-bang
182 /* Energy Star Assert Change Time register.  This determines the number
189 /* Energy Star Assert Bypass Time register.  This determines the number
198  * de-assertion of CLK_CHANGE_L[2:0] and the de-assertion of the FREEZE_L
204  * BBC clocks between the de-assertion of CLK_CHANGE_L[2:0] and the first
215 /* Keyboard Beep Counter register.  There is a free-running counter inside