Lines Matching +full:pll1 +full:- +full:div2
1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
30 * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1, in pll_recalc()
35 return clk->parent->rate * multiplier; in pll_recalc()
53 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, variable
57 .divisors = div2,
58 .nr_divisors = ARRAY_SIZE(div2),
139 CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
140 CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
141 CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
142 CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
143 CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
144 CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),
155 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
156 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
157 CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
158 CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),