Lines Matching +full:0 +full:- +full:9 +full:a +full:- +full:e
1 /* SPDX-License-Identifier: GPL-2.0 */
9 * notes on SH-X2 MMUs and 64-bit PTEs):
11 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
13 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
14 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
15 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
18 * SH-3 specific flags until all of the other unused bits have been
21 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
23 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
26 * - On 29 bit platforms, bits 31 to 29 are used for the space attributes
27 * and timing control which (together with bit 0) are moved into the
28 * old-style PTEA on the parts that support it.
30 * SH-X2 MMUs and extended PTEs
32 * SH-X2 supports an extended mode TLB with split data arrays due to the
37 * The downside to this is that we can no longer fit everything in to a 32-bit
38 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
39 * side, this gives us quite a few spare bits to play with for future usage.
42 #define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
43 #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
44 #define _PAGE_DIRTY 0x004 /* D-bit : page changed */
45 #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
46 #define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
47 #define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
48 #define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
49 #define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
50 #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
51 #define _PAGE_PROTNONE 0x200 /* software: if not present */
52 #define _PAGE_ACCESSED 0x400 /* software: page referenced */
53 #define _PAGE_SPECIAL 0x800 /* software: special page */
59 #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
60 #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
61 #define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
62 #define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
64 #define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
65 #define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
66 #define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
68 #define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
69 #define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
70 #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
72 #define _PAGE_EXT_WIRED 0x4000 /* software: Wire TLB entry */
78 #define _PAGE_PCC_MASK 0x00000000 /* No legacy PTEA support */
82 #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
83 #define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
85 /* software: moves to PTEA.SA[2:0] (Space Attributes) */
86 #define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
87 #define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
88 #define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
89 #define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
90 #define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
91 #define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
92 #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
94 #define _PAGE_PCC_MASK 0xe0000001
99 return ((x >> 28) & 0xe) | (x & 0x1); in copy_ptea_attributes()
119 # define _PAGE_FLAGS_HARD 0ULL
155 # define _PAGE_WIRED (0)
159 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
175 #if defined(CONFIG_X2TLB) /* SH-X2 TLB */
236 __pgprot(0)
238 #elif defined(CONFIG_MMU) /* SH-X TLB */
275 #define PAGE_NONE __pgprot(0)
276 #define PAGE_SHARED __pgprot(0)
277 #define PAGE_COPY __pgprot(0)
278 #define PAGE_EXECREAD __pgprot(0)
279 #define PAGE_RWX __pgprot(0)
280 #define PAGE_READONLY __pgprot(0)
281 #define PAGE_WRITEONLY __pgprot(0)
282 #define PAGE_KERNEL __pgprot(0)
283 #define PAGE_KERNEL_NOCACHE __pgprot(0)
284 #define PAGE_KERNEL_RO __pgprot(0)
287 __pgprot(0)
296 * within a page table are directly modified. Thus, the following
302 ptep->pte_high = pte.pte_high; in set_pte()
304 ptep->pte_low = pte.pte_low; in set_pte()
312 * but the define is needed for a generic inline function.)
325 #define pte_clear(mm, addr, ptep) set_pte(ptep, __pte(0))
329 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
332 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
356 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
358 * kernel permissions), we attempt to couple them a bit more sanely here.
376 * Macro and implementation to make a page protection as uncachable.
384 * Conversion functions: convert a page and protection to a page entry,
385 * and a page entry and page directory to the page they refer to.
412 #define pte_ERROR(e) \ argument
414 &(e), (e).pte_high, (e).pte_low)
415 #define pgd_ERROR(e) \ argument
416 printk("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
418 #define pte_ERROR(e) \ argument
419 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
420 #define pgd_ERROR(e) \ argument
421 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
430 * _PAGE_PROTNONE at bit 9
433 * such that bits 8 and 9 stay zero. For the 64-bit PTE case, we use the
437 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
438 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
447 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
448 * <--------------------- offset ----------------------> < type ->
451 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
452 * <------------------- zeroes --------------------> E 0 0 0 0 0 0
454 #define __swp_type(x) ((x).val & 0x1f)
456 #define __swp_entry(type, offset) ((swp_entry_t){ ((type) & 0x1f) | (offset) << 5})
458 #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
465 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
466 * <--------------- offset ----------------> 0 0 0 0 E < type -> 0
468 * E is the exclusive marker that is not stored in swap entries.
470 #define __swp_type(x) ((x).val & 0x1f)
472 #define __swp_entry(type, offset) ((swp_entry_t){((type) & 0x1f) | (offset) << 10})