Lines Matching +full:0 +full:x4321
15 UNUSED = 0,
46 { 0xa4000010, 0, 16, /* IRLMCR1 */
47 { 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
48 RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
49 { 0xa4000012, 0, 16, /* IRLMCR2 */
50 { 0, 0, 0, 0, 0, 0, 0, 0,
55 0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
66 if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000) in highlander_plat_irq_setup()
71 __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ in highlander_plat_irq_setup()
74 __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */ in highlander_plat_irq_setup()
75 __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */ in highlander_plat_irq_setup()
76 __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */ in highlander_plat_irq_setup()
77 __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */ in highlander_plat_irq_setup()
78 __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */ in highlander_plat_irq_setup()
79 __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */ in highlander_plat_irq_setup()