1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Hardware-accelerated CRC-32 variants for Linux on z Systems
6  * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9  * This CRC-32 implementation algorithm is bitreflected and processes
10  * the least-significant bit first (Little-Endian).
18 #include "crc32-vx.h"
20 /* Vector register range containing CRC-32 constants */
29  * The CRC-32 constant block contains reduction constants to fold and
32  * For the CRC-32 variants, the constants are precomputed according to
35  *	R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
36  *	R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
37  *	R3 = [(x128+32 mod P'(x) << 32)]'   << 1
38  *	R4 = [(x128-32 mod P'(x) << 32)]'   << 1
39  *	R5 = [(x64 mod P'(x) << 32)]'	    << 1
40  *	R6 = [(x32 mod P'(x) << 32)]'	    << 1
48  * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
50  *	P(x)  = 0x04C11DB7
51  *	P'(x) = 0xEDB88320
53  * CRC-32C (Castagnoli) polynomials:
55  *	P(x)  = 0x1EDC6F41
56  *	P'(x) = 0x82F63B78
60 	0x0f0e0d0c0b0a0908, 0x0706050403020100,	/* BE->LE mask */
61 	0x1c6e41596, 0x154442bd4,		/* R2, R1 */
62 	0x0ccaa009e, 0x1751997d0,		/* R4, R3 */
63 	0x0, 0x163cd6124,			/* R5 */
64 	0x0, 0x1f7011641,			/* u' */
65 	0x0, 0x1db710641			/* P'(x) << 1 */
69 	0x0f0e0d0c0b0a0908, 0x0706050403020100,	/* BE->LE mask */
70 	0x09e4addf8, 0x740eef02,		/* R2, R1 */
71 	0x14cd00bd6, 0xf20c0dfe,		/* R4, R3 */
72 	0x0, 0x0dd45aab8,			/* R5 */
73 	0x0, 0x0dea713f1,			/* u' */
74 	0x0, 0x105ec76f0			/* P'(x) << 1 */
78  * crc32_le_vgfm_generic - Compute CRC-32 (LE variant) with vector registers
79  * @crc: Initial CRC value, typically ~0.
83  * @constants: CRC-32 constant pool base pointer.
89  *	V9:	  Constant for BE->LE conversion and shift operations
90  *	V10..V14: CRC-32 constants.
94 	/* Load CRC-32 constants */  in crc32_le_vgfm_generic()
104 	fpu_vzero(0);			/* Clear V0 */  in crc32_le_vgfm_generic()
105 	fpu_vlvgf(0, crc, 3);		/* Load CRC into rightmost word */  in crc32_le_vgfm_generic()
107 	/* Load a 64-byte data chunk and XOR with CRC */  in crc32_le_vgfm_generic()
114 	fpu_vx(1, 0, 1);		/* V1 ^= CRC */  in crc32_le_vgfm_generic()
116 	size -= 64;  in crc32_le_vgfm_generic()
136 		size -= 64;  in crc32_le_vgfm_generic()
140 	 * Fold V1 to V4 into a single 128-bit value in V1.  Multiply V1 with R3  in crc32_le_vgfm_generic()
141 	 * and R4 and accumulating the next 128-bit chunk until a single 128-bit  in crc32_le_vgfm_generic()
153 		size -= 16;  in crc32_le_vgfm_generic()
158 	 * be loaded in bits 1-4 in byte element 7 of a vector register.  in crc32_le_vgfm_generic()
159 	 * Shift by 8 bytes: 0x40  in crc32_le_vgfm_generic()
160 	 * Shift by 4 bytes: 0x20  in crc32_le_vgfm_generic()
162 	fpu_vleib(9, 0x40, 7);  in crc32_le_vgfm_generic()
167 	 * doubleword to 0x1.  in crc32_le_vgfm_generic()
169 	fpu_vsrlb(0, CONST_R4R3, 9);  in crc32_le_vgfm_generic()
170 	fpu_vleig(0, 1, 0);  in crc32_le_vgfm_generic()
175 	 * multiplied by 0x1 and is then XORed with rightmost product.  in crc32_le_vgfm_generic()
178 	fpu_vgfmg(1, 0, 1);  in crc32_le_vgfm_generic()
181 	 * Now do the final 32-bit fold by multiplying the rightmost word  in crc32_le_vgfm_generic()
193 	fpu_vleib(9, 0x20, 7);		  /* Shift by words */  in crc32_le_vgfm_generic()
199 	 * Apply a Barret reduction to compute the final 32-bit CRC value.  in crc32_le_vgfm_generic()
201 	 * The input values to the Barret reduction are the degree-63 polynomial  in crc32_le_vgfm_generic()
202 	 * in V1 (R(x)), degree-32 generator polynomial, and the reduction  in crc32_le_vgfm_generic()
208 	 *    1. T1(x) = floor( R(x) / x^32 ) GF2MUL u  in crc32_le_vgfm_generic()
209 	 *    2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x)  in crc32_le_vgfm_generic()
210 	 *    3. C(x)  = R(x) XOR T2(x) mod x^32  in crc32_le_vgfm_generic()
217 	/* T1(x) = floor( R(x) / x^32 ) GF2MUL u */  in crc32_le_vgfm_generic()
234 	return crc32_le_vgfm_generic(crc, buf, size, &constants_CRC_32_LE[0]);  in crc32_le_vgfm_16()
239 	return crc32_le_vgfm_generic(crc, buf, size, &constants_CRC_32C_LE[0]);  in crc32c_le_vgfm_16()