117 struct zpci_dev {  struct
119 	struct list_head entry;		/* list of all zpci_devices, needed for hotplug, etc. */  argument
120 	struct list_head iommu_list;
121 	struct kref kref;
122 	struct rcu_head rcu;
123 	struct hotplug_slot hotplug_slot;
125 	struct mutex state_lock;	/* protect state changes */
126 	enum zpci_state state;
127 	u32		fid;		/* function ID, used by sclp */
128 	u32		fh;		/* function handle, used by insn's */
129 	u32		gisa;		/* GISA designation for passthrough */
130 	u16		vfn;		/* virtual function number */
131 	u16		pchid;		/* physical channel ID */
132 	u16		maxstbl;	/* Maximum store block size */
133 	u16		rid;		/* RID as supplied by firmware */
134 	u16		tid;		/* Topology for which RID is valid */
135 	u8		pfgid;		/* function group ID */
136 	u8		pft;		/* pci function type */
137 	u8		port;
138 	u8		fidparm;
139 	u8		dtsm;		/* Supported DT mask */
140 	u8		rid_available	: 1;
141 	u8		has_hp_slot	: 1;
142 	u8		has_resources	: 1;
143 	u8		is_physfn	: 1;
144 	u8		util_str_avail	: 1;
145 	u8		irqs_registered	: 1;
146 	u8		tid_avail	: 1;
147 	u8		reserved	: 1;
148 	unsigned int	devfn;		/* DEVFN part of the RID*/
150 	u8 pfip[CLP_PFIP_NR_SEGMENTS];	/* pci function internal path */
151 	u32 uid;			/* user defined id */
152 	u8 util_str[CLP_UTIL_STR_LEN];	/* utility string */
155 	u64		msi_addr;	/* MSI address */
156 	unsigned int	max_msi;	/* maximum number of MSI's */
157 	unsigned int	msi_first_bit;
158 	unsigned int	msi_nr_irqs;
159 	struct airq_iv *aibv;		/* adapter interrupt bit vector */
160 	unsigned long	aisb;		/* number of the summary bit */
163 	unsigned long	*dma_table;
164 	int		tlb_refresh;
166 	struct iommu_device iommu_dev;  /* IOMMU core handle */
168 	char res_name[16];
169 	bool mio_capable;
170 	struct zpci_bar_struct bars[PCI_STD_NUM_BARS];
194 static inline bool zdev_enabled(struct zpci_dev *zdev)  in zdev_enabled()  argument