25 	.macro insn_r, opcode, func3, func7, rd, rs1, rs2
26 	.insn	r \opcode, \func3, \func7, \rd, \rs1, \rs2
29 	.macro insn_i, opcode, func3, rd, rs1, simm12
30 	.insn	i \opcode, \func3, \rd, \rs1, \simm12
37 	.macro insn_r, opcode, func3, func7, rd, rs1, rs2
42 		 (.L__gpr_num_\rs1 << INSN_R_RS1_SHIFT) |	\
46 	.macro insn_i, opcode, func3, rd, rs1, simm12
50 		 (.L__gpr_num_\rs1 << INSN_I_RS1_SHIFT) |	\
63 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2)	\  argument
64 	".insn	r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
66 #define __INSN_I(opcode, func3, rd, rs1, simm12)	\  argument
67 	".insn	i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
76 "	.macro insn_r, opcode, func3, func7, rd, rs1, rs2\n"		\
81 "		 (.L__gpr_num_\\rs1 << " __stringify(INSN_R_RS1_SHIFT) ") |"  \
87 "	.macro insn_i, opcode, func3, rd, rs1, simm12\n"		\
91 "		 (.L__gpr_num_\\rs1 << " __stringify(INSN_I_RS1_SHIFT) ") |" \
101 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2)			\  argument
103 	"insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
106 #define __INSN_I(opcode, func3, rd, rs1, simm12)			\  argument
108 	"insn_i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" \
115 #define INSN_R(opcode, func3, func7, rd, rs1, rs2)		\  argument
117 		 RV_##rd, RV_##rs1, RV_##rs2)
119 #define INSN_I(opcode, func3, rd, rs1, simm12)			\  argument
121 		 RV_##rs1, RV_##simm12)
140 	       __RD(0), RS1(vaddr), RS2(asid))
144 	       __RD(0), RS1(gaddr), RS2(vmid))
148 	       RD(dest), RS1(addr), __RS2(3))
152 	       RD(dest), RS1(addr), __RS2(0))
157 	       RD(dest), RS1(addr), __RS2(0))
165 	       __RD(0), RS1(vaddr), RS2(asid))
177 	       __RD(0), RS1(vaddr), RS2(asid))
181 	       __RD(0), RS1(gaddr), RS2(vmid))
185 	       RS1(base), SIMM12(0))
189 	       RS1(base), SIMM12(1))
193 	       RS1(base), SIMM12(2))
197 	       RS1(base), SIMM12(4))