Lines Matching +full:xlen +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
45 #define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */
54 #define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */
55 #define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */
56 #define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */
78 /* Exception cause high bit - is an interrupt if set */
79 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
82 #define IRQ_S_SOFT 1
93 #define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
94 #define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0)
98 #define EXC_INST_ACCESS 1
148 #define HGATP_MODE_SV32X4 _AC(1, UL)
178 #define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT)
179 #define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \
180 (_AC(1, UL) << IRQ_S_TIMER) | \
181 (_AC(1, UL) << IRQ_S_EXT) | \
182 (_AC(1, UL) << IRQ_PMU_OVF))
206 #define ENVCFG_STCE (_AC(1, ULL) << 63)
207 #define ENVCFG_PBMTE (_AC(1, ULL) << 62)
208 #define ENVCFG_ADUE (_AC(1, ULL) << 61)
213 #define ENVCFG_CBZE (_AC(1, UL) << 7)
214 #define ENVCFG_CBCFE (_AC(1, UL) << 6)
224 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT)
226 #define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT)
228 #define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT)
230 #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
232 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
330 #define CSR_VXRM_SHIFT 1
331 #define CSR_VXSAT_MASK 1
333 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
337 /* Supervisor-Level Interrupts (AIA) */
341 /* Supervisor-Level High-Half CSRs (AIA) */
374 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
380 /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
384 /* VS-Level Interrupts (H-extension with AIA) */
388 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
422 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
426 /* Machine-Level Interrupts (AIA) */
434 /* Machine-Level High-Half CSRs (AIA) */
447 /* Scalar Crypto Extension - Entropy */
521 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
547 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
564 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\