Lines Matching +full:timer +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
28 i-cache-block-size = <64>;
29 i-cache-size = <65536>;
30 i-cache-sets = <512>;
31 d-cache-block-size = <64>;
32 d-cache-size = <65536>;
33 d-cache-sets = <512>;
34 next-level-cache = <&l2_cache>;
35 mmu-type = "riscv,sv39";
37 cpu0_intc: interrupt-controller {
38 compatible = "riscv,cpu-intc";
39 interrupt-controller;
40 #interrupt-cells = <1>;
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
52 i-cache-block-size = <64>;
53 i-cache-size = <65536>;
54 i-cache-sets = <512>;
55 d-cache-block-size = <64>;
56 d-cache-size = <65536>;
57 d-cache-sets = <512>;
58 next-level-cache = <&l2_cache>;
59 mmu-type = "riscv,sv39";
61 cpu1_intc: interrupt-controller {
62 compatible = "riscv,cpu-intc";
63 interrupt-controller;
64 #interrupt-cells = <1>;
72 riscv,isa-base = "rv64i";
73 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
76 i-cache-block-size = <64>;
77 i-cache-size = <65536>;
78 i-cache-sets = <512>;
79 d-cache-block-size = <64>;
80 d-cache-size = <65536>;
81 d-cache-sets = <512>;
82 next-level-cache = <&l2_cache>;
83 mmu-type = "riscv,sv39";
85 cpu2_intc: interrupt-controller {
86 compatible = "riscv,cpu-intc";
87 interrupt-controller;
88 #interrupt-cells = <1>;
96 riscv,isa-base = "rv64i";
97 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
100 i-cache-block-size = <64>;
101 i-cache-size = <65536>;
102 i-cache-sets = <512>;
103 d-cache-block-size = <64>;
104 d-cache-size = <65536>;
105 d-cache-sets = <512>;
106 next-level-cache = <&l2_cache>;
107 mmu-type = "riscv,sv39";
109 cpu3_intc: interrupt-controller {
110 compatible = "riscv,cpu-intc";
111 interrupt-controller;
112 #interrupt-cells = <1>;
116 l2_cache: l2-cache {
118 cache-block-size = <64>;
119 cache-level = <2>;
120 cache-size = <1048576>;
121 cache-sets = <1024>;
122 cache-unified;
128 riscv,event-to-mhpmcounters =
145 riscv,event-to-mhpmevent =
162 riscv,raw-event-to-mhpmcounters =
208 compatible = "fixed-clock";
209 clock-output-names = "osc_24m";
210 #clock-cells = <0>;
213 osc_32k: 32k-oscillator {
214 compatible = "fixed-clock";
215 clock-output-names = "osc_32k";
216 #clock-cells = <0>;
219 aonsys_clk: clock-73728000 {
220 compatible = "fixed-clock";
221 clock-frequency = <73728000>;
222 clock-output-names = "aonsys_clk";
223 #clock-cells = <0>;
226 stmmac_axi_config: stmmac-axi-config {
233 compatible = "simple-bus";
234 interrupt-parent = <&plic>;
235 #address-cells = <2>;
236 #size-cells = <2>;
237 dma-noncoherent;
240 plic: interrupt-controller@ffd8000000 {
241 compatible = "thead,th1520-plic", "thead,c900-plic";
243 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
247 interrupt-controller;
248 #address-cells = <0>;
249 #interrupt-cells = <2>;
253 clint: timer@ffdc000000 {
254 compatible = "thead,th1520-clint", "thead,c900-clint";
256 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
263 compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
267 #address-cells = <1>;
268 #size-cells = <0>;
273 compatible = "snps,dw-apb-uart";
277 clock-names = "baudclk", "apb_pclk";
278 reg-shift = <2>;
279 reg-io-width = <4>;
284 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
286 reg-names = "dwmac", "apb";
288 interrupt-names = "macirq";
290 clock-names = "stmmaceth", "pclk";
292 snps,fixed-burst;
293 snps,multicast-filter-bins = <64>;
294 snps,perfect-filter-entries = <32>;
295 snps,axi-config = <&stmmac_axi_config>;
299 compatible = "snps,dwmac-mdio";
300 #address-cells = <1>;
301 #size-cells = <0>;
306 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
308 reg-names = "dwmac", "apb";
310 interrupt-names = "macirq";
312 clock-names = "stmmaceth", "pclk";
314 snps,fixed-burst;
315 snps,multicast-filter-bins = <64>;
316 snps,perfect-filter-entries = <32>;
317 snps,axi-config = <&stmmac_axi_config>;
321 compatible = "snps,dwmac-mdio";
322 #address-cells = <1>;
323 #size-cells = <0>;
328 compatible = "thead,th1520-dwcmshc";
332 clock-names = "core";
337 compatible = "thead,th1520-dwcmshc";
341 clock-names = "core";
346 compatible = "thead,th1520-dwcmshc";
350 clock-names = "core";
355 compatible = "snps,dw-apb-uart";
359 clock-names = "baudclk", "apb_pclk";
360 reg-shift = <2>;
361 reg-io-width = <4>;
366 compatible = "snps,dw-apb-uart";
370 clock-names = "baudclk", "apb_pclk";
371 reg-shift = <2>;
372 reg-io-width = <4>;
377 compatible = "snps,dw-apb-gpio";
379 #address-cells = <1>;
380 #size-cells = <0>;
382 clock-names = "bus";
384 gpio2: gpio-controller@0 {
385 compatible = "snps,dw-apb-gpio-port";
386 gpio-controller;
387 #gpio-cells = <2>;
389 gpio-ranges = <&padctrl0_apsys 0 0 32>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
398 compatible = "snps,dw-apb-gpio";
400 #address-cells = <1>;
401 #size-cells = <0>;
403 clock-names = "bus";
405 gpio3: gpio-controller@0 {
406 compatible = "snps,dw-apb-gpio-port";
407 gpio-controller;
408 #gpio-cells = <2>;
410 gpio-ranges = <&padctrl0_apsys 0 32 23>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
419 compatible = "thead,th1520-pinctrl";
422 thead,pad-group = <2>;
426 compatible = "snps,dw-apb-gpio";
428 #address-cells = <1>;
429 #size-cells = <0>;
431 clock-names = "bus";
433 gpio0: gpio-controller@0 {
434 compatible = "snps,dw-apb-gpio-port";
435 gpio-controller;
436 #gpio-cells = <2>;
438 gpio-ranges = <&padctrl1_apsys 0 0 32>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
447 compatible = "snps,dw-apb-gpio";
449 #address-cells = <1>;
450 #size-cells = <0>;
452 clock-names = "bus";
454 gpio1: gpio-controller@0 {
455 compatible = "snps,dw-apb-gpio-port";
456 gpio-controller;
457 #gpio-cells = <2>;
459 gpio-ranges = <&padctrl1_apsys 0 32 31>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
468 compatible = "thead,th1520-pinctrl";
471 thead,pad-group = <3>;
475 compatible = "snps,dw-apb-uart";
479 clock-names = "baudclk", "apb_pclk";
480 reg-shift = <2>;
481 reg-io-width = <4>;
485 clk: clock-controller@ffef010000 {
486 compatible = "thead,th1520-clk-ap";
489 #clock-cells = <1>;
492 dmac0: dma-controller@ffefc00000 {
493 compatible = "snps,axi-dma-1.01a";
497 clock-names = "core-clk", "cfgr-clk";
498 #dma-cells = <1>;
499 dma-channels = <4>;
500 snps,block-size = <65536 65536 65536 65536>;
502 snps,dma-masters = <1>;
503 snps,data-width = <4>;
504 snps,axi-max-burst-len = <16>;
508 timer0: timer@ffefc32000 {
509 compatible = "snps,dw-apb-timer";
512 clock-names = "timer";
517 timer1: timer@ffefc32014 {
518 compatible = "snps,dw-apb-timer";
521 clock-names = "timer";
526 timer2: timer@ffefc32028 {
527 compatible = "snps,dw-apb-timer";
530 clock-names = "timer";
535 timer3: timer@ffefc3203c {
536 compatible = "snps,dw-apb-timer";
539 clock-names = "timer";
545 compatible = "snps,dw-apb-uart";
549 clock-names = "baudclk", "apb_pclk";
550 reg-shift = <2>;
551 reg-io-width = <4>;
556 compatible = "snps,dw-apb-uart";
560 clock-names = "baudclk", "apb_pclk";
561 reg-shift = <2>;
562 reg-io-width = <4>;
566 timer4: timer@ffffc33000 {
567 compatible = "snps,dw-apb-timer";
570 clock-names = "timer";
575 timer5: timer@ffffc33014 {
576 compatible = "snps,dw-apb-timer";
579 clock-names = "timer";
584 timer6: timer@ffffc33028 {
585 compatible = "snps,dw-apb-timer";
588 clock-names = "timer";
593 timer7: timer@ffffc3303c {
594 compatible = "snps,dw-apb-timer";
597 clock-names = "timer";
603 compatible = "thead,th1520-mbox";
608 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2";
611 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1",
612 "clk-remote-icu2";
613 interrupt-parent = <&plic>;
615 #mbox-cells = <1>;
619 compatible = "snps,dw-apb-gpio";
621 #address-cells = <1>;
622 #size-cells = <0>;
624 aogpio: gpio-controller@0 {
625 compatible = "snps,dw-apb-gpio-port";
626 gpio-controller;
627 #gpio-cells = <2>;
629 gpio-ranges = <&padctrl_aosys 0 9 16>;
631 interrupt-controller;
632 #interrupt-cells = <2>;
638 compatible = "thead,th1520-pinctrl";
641 thead,pad-group = <1>;
645 compatible = "snps,dw-apb-gpio";
647 #address-cells = <1>;
648 #size-cells = <0>;
650 gpio4: gpio-controller@0 {
651 compatible = "snps,dw-apb-gpio-port";
652 gpio-controller;
653 #gpio-cells = <2>;
655 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
657 interrupt-controller;
658 #interrupt-cells = <2>;