Lines Matching +full:jh7110 +full:- +full:syscrg
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
26 i-cache-block-size = <64>;
27 i-cache-sets = <64>;
28 i-cache-size = <16384>;
29 next-level-cache = <&ccache>;
31 riscv,isa-base = "rv64i";
32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
44 compatible = "sifive,u74-mc", "riscv";
46 d-cache-block-size = <64>;
47 d-cache-sets = <64>;
48 d-cache-size = <32768>;
49 d-tlb-sets = <1>;
50 d-tlb-size = <40>;
52 i-cache-block-size = <64>;
53 i-cache-sets = <64>;
54 i-cache-size = <32768>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <40>;
57 mmu-type = "riscv,sv39";
58 next-level-cache = <&ccache>;
60 riscv,isa-base = "rv64i";
61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
63 tlb-split;
64 operating-points-v2 = <&cpu_opp>;
65 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
66 clock-names = "cpu";
67 #cooling-cells = <2>;
69 cpu1_intc: interrupt-controller {
70 compatible = "riscv,cpu-intc";
71 interrupt-controller;
72 #interrupt-cells = <1>;
77 compatible = "sifive,u74-mc", "riscv";
79 d-cache-block-size = <64>;
80 d-cache-sets = <64>;
81 d-cache-size = <32768>;
82 d-tlb-sets = <1>;
83 d-tlb-size = <40>;
85 i-cache-block-size = <64>;
86 i-cache-sets = <64>;
87 i-cache-size = <32768>;
88 i-tlb-sets = <1>;
89 i-tlb-size = <40>;
90 mmu-type = "riscv,sv39";
91 next-level-cache = <&ccache>;
93 riscv,isa-base = "rv64i";
94 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
96 tlb-split;
97 operating-points-v2 = <&cpu_opp>;
98 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
99 clock-names = "cpu";
100 #cooling-cells = <2>;
102 cpu2_intc: interrupt-controller {
103 compatible = "riscv,cpu-intc";
104 interrupt-controller;
105 #interrupt-cells = <1>;
110 compatible = "sifive,u74-mc", "riscv";
112 d-cache-block-size = <64>;
113 d-cache-sets = <64>;
114 d-cache-size = <32768>;
115 d-tlb-sets = <1>;
116 d-tlb-size = <40>;
118 i-cache-block-size = <64>;
119 i-cache-sets = <64>;
120 i-cache-size = <32768>;
121 i-tlb-sets = <1>;
122 i-tlb-size = <40>;
123 mmu-type = "riscv,sv39";
124 next-level-cache = <&ccache>;
126 riscv,isa-base = "rv64i";
127 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
129 tlb-split;
130 operating-points-v2 = <&cpu_opp>;
131 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
132 clock-names = "cpu";
133 #cooling-cells = <2>;
135 cpu3_intc: interrupt-controller {
136 compatible = "riscv,cpu-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
143 compatible = "sifive,u74-mc", "riscv";
145 d-cache-block-size = <64>;
146 d-cache-sets = <64>;
147 d-cache-size = <32768>;
148 d-tlb-sets = <1>;
149 d-tlb-size = <40>;
151 i-cache-block-size = <64>;
152 i-cache-sets = <64>;
153 i-cache-size = <32768>;
154 i-tlb-sets = <1>;
155 i-tlb-size = <40>;
156 mmu-type = "riscv,sv39";
157 next-level-cache = <&ccache>;
159 riscv,isa-base = "rv64i";
160 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
162 tlb-split;
163 operating-points-v2 = <&cpu_opp>;
164 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
165 clock-names = "cpu";
166 #cooling-cells = <2>;
168 cpu4_intc: interrupt-controller {
169 compatible = "riscv,cpu-intc";
170 interrupt-controller;
171 #interrupt-cells = <1>;
175 cpu-map {
200 cpu_opp: opp-table-0 {
201 compatible = "operating-points-v2";
202 opp-shared;
203 opp-375000000 {
204 opp-hz = /bits/ 64 <375000000>;
205 opp-microvolt = <800000>;
207 opp-500000000 {
208 opp-hz = /bits/ 64 <500000000>;
209 opp-microvolt = <800000>;
211 opp-750000000 {
212 opp-hz = /bits/ 64 <750000000>;
213 opp-microvolt = <800000>;
215 opp-1500000000 {
216 opp-hz = /bits/ 64 <1500000000>;
217 opp-microvolt = <1040000>;
221 thermal-zones {
222 cpu-thermal {
223 polling-delay-passive = <250>;
224 polling-delay = <15000>;
226 thermal-sensors = <&sfctemp>;
228 cooling-maps {
231 cooling-device =
240 cpu_alert0: cpu-alert0 {
247 cpu-crit {
257 dvp_clk: dvp-clock {
258 compatible = "fixed-clock";
259 clock-output-names = "dvp_clk";
260 #clock-cells = <0>;
262 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
263 compatible = "fixed-clock";
264 clock-output-names = "gmac0_rgmii_rxin";
265 #clock-cells = <0>;
268 gmac0_rmii_refin: gmac0-rmii-refin-clock {
269 compatible = "fixed-clock";
270 clock-output-names = "gmac0_rmii_refin";
271 #clock-cells = <0>;
274 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
275 compatible = "fixed-clock";
276 clock-output-names = "gmac1_rgmii_rxin";
277 #clock-cells = <0>;
280 gmac1_rmii_refin: gmac1-rmii-refin-clock {
281 compatible = "fixed-clock";
282 clock-output-names = "gmac1_rmii_refin";
283 #clock-cells = <0>;
286 hdmitx0_pixelclk: hdmitx0-pixel-clock {
287 compatible = "fixed-clock";
288 clock-output-names = "hdmitx0_pixelclk";
289 #clock-cells = <0>;
292 i2srx_bclk_ext: i2srx-bclk-ext-clock {
293 compatible = "fixed-clock";
294 clock-output-names = "i2srx_bclk_ext";
295 #clock-cells = <0>;
298 i2srx_lrck_ext: i2srx-lrck-ext-clock {
299 compatible = "fixed-clock";
300 clock-output-names = "i2srx_lrck_ext";
301 #clock-cells = <0>;
304 i2stx_bclk_ext: i2stx-bclk-ext-clock {
305 compatible = "fixed-clock";
306 clock-output-names = "i2stx_bclk_ext";
307 #clock-cells = <0>;
310 i2stx_lrck_ext: i2stx-lrck-ext-clock {
311 compatible = "fixed-clock";
312 clock-output-names = "i2stx_lrck_ext";
313 #clock-cells = <0>;
316 mclk_ext: mclk-ext-clock {
317 compatible = "fixed-clock";
318 clock-output-names = "mclk_ext";
319 #clock-cells = <0>;
323 compatible = "fixed-clock";
324 clock-output-names = "osc";
325 #clock-cells = <0>;
328 rtc_osc: rtc-oscillator {
329 compatible = "fixed-clock";
330 clock-output-names = "rtc_osc";
331 #clock-cells = <0>;
334 stmmac_axi_setup: stmmac-axi-config {
341 tdm_ext: tdm-ext-clock {
342 compatible = "fixed-clock";
343 clock-output-names = "tdm_ext";
344 #clock-cells = <0>;
348 compatible = "simple-bus";
349 interrupt-parent = <&plic>;
350 #address-cells = <2>;
351 #size-cells = <2>;
355 compatible = "starfive,jh7110-clint", "sifive,clint0";
357 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
364 ccache: cache-controller@2010000 {
365 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
368 cache-block-size = <64>;
369 cache-level = <2>;
370 cache-sets = <2048>;
371 cache-size = <2097152>;
372 cache-unified;
375 plic: interrupt-controller@c000000 {
376 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
378 interrupts-extended = <&cpu0_intc 11>,
383 interrupt-controller;
384 #interrupt-cells = <1>;
385 #address-cells = <0>;
390 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
392 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
393 <&syscrg JH7110_SYSCLK_UART0_APB>;
394 clock-names = "baudclk", "apb_pclk";
395 resets = <&syscrg JH7110_SYSRST_UART0_APB>,
396 <&syscrg JH7110_SYSRST_UART0_CORE>;
398 reg-io-width = <4>;
399 reg-shift = <2>;
404 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
406 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
407 <&syscrg JH7110_SYSCLK_UART1_APB>;
408 clock-names = "baudclk", "apb_pclk";
409 resets = <&syscrg JH7110_SYSRST_UART1_APB>,
410 <&syscrg JH7110_SYSRST_UART1_CORE>;
412 reg-io-width = <4>;
413 reg-shift = <2>;
418 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
420 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
421 <&syscrg JH7110_SYSCLK_UART2_APB>;
422 clock-names = "baudclk", "apb_pclk";
423 resets = <&syscrg JH7110_SYSRST_UART2_APB>,
424 <&syscrg JH7110_SYSRST_UART2_CORE>;
426 reg-io-width = <4>;
427 reg-shift = <2>;
432 compatible = "snps,designware-i2c";
434 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
435 clock-names = "ref";
436 resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
438 #address-cells = <1>;
439 #size-cells = <0>;
444 compatible = "snps,designware-i2c";
446 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
447 clock-names = "ref";
448 resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
450 #address-cells = <1>;
451 #size-cells = <0>;
456 compatible = "snps,designware-i2c";
458 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
459 clock-names = "ref";
460 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
462 #address-cells = <1>;
463 #size-cells = <0>;
470 clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
471 <&syscrg JH7110_SYSCLK_SPI0_APB>;
472 clock-names = "sspclk", "apb_pclk";
473 resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
475 arm,primecell-periphid = <0x00041022>;
476 num-cs = <1>;
477 #address-cells = <1>;
478 #size-cells = <0>;
485 clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
486 <&syscrg JH7110_SYSCLK_SPI1_APB>;
487 clock-names = "sspclk", "apb_pclk";
488 resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
490 arm,primecell-periphid = <0x00041022>;
491 num-cs = <1>;
492 #address-cells = <1>;
493 #size-cells = <0>;
500 clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
501 <&syscrg JH7110_SYSCLK_SPI2_APB>;
502 clock-names = "sspclk", "apb_pclk";
503 resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
505 arm,primecell-periphid = <0x00041022>;
506 num-cs = <1>;
507 #address-cells = <1>;
508 #size-cells = <0>;
513 compatible = "starfive,jh7110-tdm";
515 clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
516 <&syscrg JH7110_SYSCLK_TDM_APB>,
517 <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
518 <&syscrg JH7110_SYSCLK_TDM_TDM>,
519 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
521 clock-names = "tdm_ahb", "tdm_apb",
524 resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
525 <&syscrg JH7110_SYSRST_TDM_APB>,
526 <&syscrg JH7110_SYSRST_TDM_CORE>;
528 dma-names = "rx","tx";
529 #sound-dai-cells = <0>;
534 compatible = "starfive,jh7110-i2srx";
536 clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
537 <&syscrg JH7110_SYSCLK_I2SRX_APB>,
538 <&syscrg JH7110_SYSCLK_MCLK>,
539 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
541 <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
542 <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
545 clock-names = "i2sclk", "apb", "mclk",
548 resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
549 <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
551 dma-names = "tx", "rx";
553 #sound-dai-cells = <0>;
558 compatible = "starfive,jh7110-pwmdac";
560 clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
561 <&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
562 clock-names = "apb", "core";
563 resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
565 dma-names = "tx";
566 #sound-dai-cells = <0>;
571 compatible = "starfive,jh7110-usb";
573 #address-cells = <1>;
574 #size-cells = <1>;
575 starfive,stg-syscon = <&stg_syscon 0x4>;
581 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
586 reset-names = "pwrup", "apb", "axi", "utmi_apb";
594 reg-names = "otg", "xhci", "dev";
596 interrupt-names = "host", "peripheral", "otg";
598 phy-names = "cdns3,usb2-phy";
603 compatible = "starfive,jh7110-usb-phy";
605 clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
607 clock-names = "125m", "app_125m";
608 #phy-cells = <0>;
612 compatible = "starfive,jh7110-pcie-phy";
614 #phy-cells = <0>;
618 compatible = "starfive,jh7110-pcie-phy";
620 #phy-cells = <0>;
623 stgcrg: clock-controller@10230000 {
624 compatible = "starfive,jh7110-stgcrg";
627 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
628 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
629 <&syscrg JH7110_SYSCLK_USB_125M>,
630 <&syscrg JH7110_SYSCLK_CPU_BUS>,
631 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
632 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
633 <&syscrg JH7110_SYSCLK_APB_BUS>;
634 clock-names = "osc", "hifi4_core",
638 #clock-cells = <1>;
639 #reset-cells = <1>;
643 compatible = "starfive,jh7110-stg-syscon", "syscon";
648 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
650 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
651 <&syscrg JH7110_SYSCLK_UART3_APB>;
652 clock-names = "baudclk", "apb_pclk";
653 resets = <&syscrg JH7110_SYSRST_UART3_APB>,
654 <&syscrg JH7110_SYSRST_UART3_CORE>;
656 reg-io-width = <4>;
657 reg-shift = <2>;
662 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
664 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
665 <&syscrg JH7110_SYSCLK_UART4_APB>;
666 clock-names = "baudclk", "apb_pclk";
667 resets = <&syscrg JH7110_SYSRST_UART4_APB>,
668 <&syscrg JH7110_SYSRST_UART4_CORE>;
670 reg-io-width = <4>;
671 reg-shift = <2>;
676 compatible = "starfive,jh7110-uart", "snps,dw-apb-uart";
678 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
679 <&syscrg JH7110_SYSCLK_UART5_APB>;
680 clock-names = "baudclk", "apb_pclk";
681 resets = <&syscrg JH7110_SYSRST_UART5_APB>,
682 <&syscrg JH7110_SYSRST_UART5_CORE>;
684 reg-io-width = <4>;
685 reg-shift = <2>;
690 compatible = "snps,designware-i2c";
692 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
693 clock-names = "ref";
694 resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
696 #address-cells = <1>;
697 #size-cells = <0>;
702 compatible = "snps,designware-i2c";
704 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
705 clock-names = "ref";
706 resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
708 #address-cells = <1>;
709 #size-cells = <0>;
714 compatible = "snps,designware-i2c";
716 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
717 clock-names = "ref";
718 resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
720 #address-cells = <1>;
721 #size-cells = <0>;
726 compatible = "snps,designware-i2c";
728 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
729 clock-names = "ref";
730 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
732 #address-cells = <1>;
733 #size-cells = <0>;
740 clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
741 <&syscrg JH7110_SYSCLK_SPI3_APB>;
742 clock-names = "sspclk", "apb_pclk";
743 resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
745 arm,primecell-periphid = <0x00041022>;
746 num-cs = <1>;
747 #address-cells = <1>;
748 #size-cells = <0>;
755 clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
756 <&syscrg JH7110_SYSCLK_SPI4_APB>;
757 clock-names = "sspclk", "apb_pclk";
758 resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
760 arm,primecell-periphid = <0x00041022>;
761 num-cs = <1>;
762 #address-cells = <1>;
763 #size-cells = <0>;
770 clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
771 <&syscrg JH7110_SYSCLK_SPI5_APB>;
772 clock-names = "sspclk", "apb_pclk";
773 resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
775 arm,primecell-periphid = <0x00041022>;
776 num-cs = <1>;
777 #address-cells = <1>;
778 #size-cells = <0>;
785 clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
786 <&syscrg JH7110_SYSCLK_SPI6_APB>;
787 clock-names = "sspclk", "apb_pclk";
788 resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
790 arm,primecell-periphid = <0x00041022>;
791 num-cs = <1>;
792 #address-cells = <1>;
793 #size-cells = <0>;
798 compatible = "starfive,jh7110-i2stx0";
800 clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
801 <&syscrg JH7110_SYSCLK_I2STX0_APB>,
802 <&syscrg JH7110_SYSCLK_MCLK>,
803 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
805 clock-names = "i2sclk", "apb", "mclk",
807 resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
808 <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
810 dma-names = "tx";
811 #sound-dai-cells = <0>;
816 compatible = "starfive,jh7110-i2stx1";
818 clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
819 <&syscrg JH7110_SYSCLK_I2STX1_APB>,
820 <&syscrg JH7110_SYSCLK_MCLK>,
821 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
823 <&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
824 <&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
827 clock-names = "i2sclk", "apb", "mclk",
830 resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
831 <&syscrg JH7110_SYSRST_I2STX1_BCLK>;
833 dma-names = "tx";
834 #sound-dai-cells = <0>;
839 compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
841 clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
842 resets = <&syscrg JH7110_SYSRST_PWM_APB>;
843 #pwm-cells = <3>;
847 sfctemp: temperature-sensor@120e0000 {
848 compatible = "starfive,jh7110-temp";
850 clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
851 <&syscrg JH7110_SYSCLK_TEMP_APB>;
852 clock-names = "sense", "bus";
853 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
854 <&syscrg JH7110_SYSRST_TEMP_APB>;
855 reset-names = "sense", "bus";
856 #thermal-sensor-cells = <0>;
860 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
864 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
865 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
866 <&syscrg JH7110_SYSCLK_QSPI_APB>;
867 clock-names = "ref", "ahb", "apb";
868 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
869 <&syscrg JH7110_SYSRST_QSPI_AHB>,
870 <&syscrg JH7110_SYSRST_QSPI_REF>;
871 reset-names = "qspi", "qspi-ocp", "rstc_ref";
872 cdns,fifo-depth = <256>;
873 cdns,fifo-width = <4>;
874 cdns,trigger-address = <0x0>;
878 syscrg: clock-controller@13020000 { label
879 compatible = "starfive,jh7110-syscrg";
889 clock-names = "osc", "gmac1_rmii_refin",
895 #clock-cells = <1>;
896 #reset-cells = <1>;
900 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
903 pllclk: clock-controller {
904 compatible = "starfive,jh7110-pll";
906 #clock-cells = <1>;
911 compatible = "starfive,jh7110-sys-pinctrl";
913 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
914 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
916 interrupt-controller;
917 #interrupt-cells = <2>;
918 gpio-controller;
919 #gpio-cells = <2>;
923 compatible = "starfive,jh7110-wdt";
925 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
926 <&syscrg JH7110_SYSCLK_WDT_CORE>;
927 clock-names = "apb", "core";
928 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
929 <&syscrg JH7110_SYSRST_WDT_CORE>;
933 compatible = "starfive,jh7110-crypto";
937 clock-names = "hclk", "ahb";
941 dma-names = "tx", "rx";
944 sdma: dma-controller@16008000 {
946 arm,primecell-periphid = <0x00041080>;
950 clock-names = "apb_pclk";
952 lli-bus-interface-ahb1;
953 mem-bus-interface-ahb1;
954 memcpy-burst-size = <256>;
955 memcpy-bus-width = <32>;
956 #dma-cells = <2>;
960 compatible = "starfive,jh7110-trng";
964 clock-names = "hclk", "ahb";
970 compatible = "starfive,jh7110-mmc";
972 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
973 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
974 clock-names = "biu","ciu";
975 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
976 reset-names = "reset";
978 fifo-depth = <32>;
979 fifo-watermark-aligned;
980 data-addr = <0>;
986 compatible = "starfive,jh7110-mmc";
988 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
989 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
990 clock-names = "biu","ciu";
991 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
992 reset-names = "reset";
994 fifo-depth = <32>;
995 fifo-watermark-aligned;
996 data-addr = <0>;
1002 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
1006 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
1008 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
1009 clock-names = "stmmaceth", "pclk", "ptp_ref",
1013 reset-names = "stmmaceth", "ahb";
1015 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1016 rx-fifo-depth = <2048>;
1017 tx-fifo-depth = <2048>;
1018 snps,multicast-filter-bins = <64>;
1019 snps,perfect-filter-entries = <256>;
1020 snps,fixed-burst;
1021 snps,no-pbl-x8;
1023 snps,axi-config = <&stmmac_axi_setup>;
1025 snps,en-tx-lpi-clockgating;
1033 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
1035 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
1036 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
1037 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
1038 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
1039 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
1040 clock-names = "stmmaceth", "pclk", "ptp_ref",
1042 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
1043 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
1044 reset-names = "stmmaceth", "ahb";
1046 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1047 rx-fifo-depth = <2048>;
1048 tx-fifo-depth = <2048>;
1049 snps,multicast-filter-bins = <64>;
1050 snps,perfect-filter-entries = <256>;
1051 snps,fixed-burst;
1052 snps,no-pbl-x8;
1054 snps,axi-config = <&stmmac_axi_setup>;
1056 snps,en-tx-lpi-clockgating;
1063 dma: dma-controller@16050000 {
1064 compatible = "starfive,jh7110-axi-dma";
1068 clock-names = "core-clk", "cfgr-clk";
1072 #dma-cells = <1>;
1073 dma-channels = <4>;
1074 snps,dma-masters = <1>;
1075 snps,data-width = <3>;
1076 snps,block-size = <65536 65536 65536 65536>;
1078 snps,axi-max-burst-len = <16>;
1081 aoncrg: clock-controller@17000000 {
1082 compatible = "starfive,jh7110-aoncrg";
1086 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
1087 <&syscrg JH7110_SYSCLK_APB_BUS>,
1088 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
1090 clock-names = "osc", "gmac0_rmii_refin",
1094 #clock-cells = <1>;
1095 #reset-cells = <1>;
1099 compatible = "starfive,jh7110-aon-syscon", "syscon";
1101 #power-domain-cells = <1>;
1105 compatible = "starfive,jh7110-aon-pinctrl";
1109 interrupt-controller;
1110 #interrupt-cells = <2>;
1111 gpio-controller;
1112 #gpio-cells = <2>;
1115 pwrc: power-controller@17030000 {
1116 compatible = "starfive,jh7110-pmu";
1119 #power-domain-cells = <1>;
1123 compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
1131 clock-names = "sys_clk", "p_clk",
1140 reset-names = "sys", "reg_bank",
1144 phy-names = "dphy";
1148 ispcrg: clock-controller@19810000 {
1149 compatible = "starfive,jh7110-ispcrg";
1151 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1152 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
1153 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
1155 clock-names = "isp_top_core", "isp_top_axi",
1157 resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
1158 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
1159 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
1160 #clock-cells = <1>;
1161 #reset-cells = <1>;
1162 power-domains = <&pwrc JH7110_PD_ISP>;
1166 compatible = "starfive,jh7110-dphy-rx";
1171 clock-names = "cfg", "ref", "tx";
1174 power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>;
1175 #phy-cells = <0>;
1179 compatible = "starfive,jh7110-camss";
1182 reg-names = "syscon", "isp";
1188 <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1189 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>;
1190 clock-names = "apb_func", "wrapper_clk_c", "dvp_inv",
1197 <&syscrg JH7110_SYSRST_ISP_TOP>,
1198 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>;
1199 reset-names = "wrapper_p", "wrapper_c", "axird",
1201 power-domains = <&pwrc JH7110_PD_ISP>;
1206 voutcrg: clock-controller@295c0000 {
1207 compatible = "starfive,jh7110-voutcrg";
1209 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
1210 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
1211 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
1212 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
1213 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
1215 clock-names = "vout_src", "vout_top_ahb",
1218 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
1219 #clock-cells = <1>;
1220 #reset-cells = <1>;
1221 power-domains = <&pwrc JH7110_PD_VOUT>;
1225 compatible = "starfive,jh7110-pcie";
1228 reg-names = "cfg", "apb";
1229 linux,pci-domain = <0>;
1230 #address-cells = <3>;
1231 #size-cells = <2>;
1232 #interrupt-cells = <1>;
1236 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1237 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
1241 msi-controller;
1243 starfive,stg-syscon = <&stg_syscon>;
1244 bus-range = <0x0 0xff>;
1245 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1249 clock-names = "noc", "tl", "axi_mst0", "apb";
1256 reset-names = "mst0", "slv0", "slv", "brg",
1260 pcie_intc0: interrupt-controller {
1261 #address-cells = <0>;
1262 #interrupt-cells = <1>;
1263 interrupt-controller;
1268 compatible = "starfive,jh7110-pcie";
1271 reg-names = "cfg", "apb";
1272 linux,pci-domain = <1>;
1273 #address-cells = <3>;
1274 #size-cells = <2>;
1275 #interrupt-cells = <1>;
1279 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1280 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
1284 msi-controller;
1286 starfive,stg-syscon = <&stg_syscon>;
1287 bus-range = <0x0 0xff>;
1288 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1292 clock-names = "noc", "tl", "axi_mst0", "apb";
1299 reset-names = "mst0", "slv0", "slv", "brg",
1303 pcie_intc1: interrupt-controller {
1304 #address-cells = <0>;
1305 #interrupt-cells = <1>;
1306 interrupt-controller;