Lines Matching +full:inverted +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
29 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
33 #address-cells = <1>;
34 #size-cells = <0>;
35 compatible = "snps,dwmac-mdio";
37 phy1: ethernet-phy@1 {
52 rx-internal-delay-ps = <1500>;
53 motorcomm,rx-clk-drv-microamp = <2910>;
54 motorcomm,rx-data-drv-microamp = <2910>;
55 motorcomm,tx-clk-adj-enabled;
56 motorcomm,tx-clk-10-inverted;
57 motorcomm,tx-clk-100-inverted;
58 motorcomm,tx-clk-1000-inverted;
62 rx-internal-delay-ps = <0>;
63 tx-internal-delay-ps = <300>;
64 motorcomm,rx-clk-drv-microamp = <2910>;
65 motorcomm,rx-data-drv-microamp = <2910>;
66 motorcomm,tx-clk-adj-enabled;
67 motorcomm,tx-clk-10-inverted;
68 motorcomm,tx-clk-100-inverted;
84 usb0_pins: usb0-0 {
85 vbus-pins {
89 bias-disable;
90 input-disable;
91 input-schmitt-disable;
92 slew-rate = <0>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&usb0_pins>;