Lines Matching +full:0 +full:- +full:7
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
17 #address-cells = <2>;
18 #size-cells = <2>;
19 dma-noncoherent;
26 compatible = "fixed-clock";
27 clock-output-names = "cgi_main";
28 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-output-names = "cgi_dpll0";
34 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-output-names = "cgi_dpll1";
40 #clock-cells = <0>;
44 compatible = "simple-bus";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 interrupt-parent = <&intc>;
51 compatible = "snps,designware-i2c";
52 reg = <0x70 0x30005000 0x0 0x1000>;
53 #address-cells = <1>;
54 #size-cells = <0>;
56 clock-names = "ref";
57 clock-frequency = <100000>;
64 compatible = "snps,designware-i2c";
65 reg = <0x70 0x30006000 0x0 0x1000>;
66 #address-cells = <1>;
67 #size-cells = <0>;
69 clock-names = "ref";
70 clock-frequency = <100000>;
77 compatible = "snps,designware-i2c";
78 reg = <0x70 0x30007000 0x0 0x1000>;
79 #address-cells = <1>;
80 #size-cells = <0>;
82 clock-names = "ref";
83 clock-frequency = <100000>;
90 compatible = "snps,designware-i2c";
91 reg = <0x70 0x30008000 0x0 0x1000>;
92 #address-cells = <1>;
93 #size-cells = <0>;
95 clock-names = "ref";
96 clock-frequency = <100000>;
103 compatible = "snps,dw-apb-gpio";
104 reg = <0x70 0x30009000 0x0 0x400>;
105 #address-cells = <1>;
106 #size-cells = <0>;
109 clock-names = "bus", "db";
111 port0a: gpio-controller@0 {
112 compatible = "snps,dw-apb-gpio-port";
113 gpio-controller;
114 #gpio-cells = <2>;
116 reg = <0>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 interrupt-parent = <&intc>;
125 compatible = "snps,dw-apb-gpio";
126 reg = <0x70 0x3000a000 0x0 0x400>;
127 #address-cells = <1>;
128 #size-cells = <0>;
131 clock-names = "bus", "db";
133 port1a: gpio-controller@0 {
134 compatible = "snps,dw-apb-gpio-port";
135 gpio-controller;
136 #gpio-cells = <2>;
138 reg = <0>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 interrupt-parent = <&intc>;
147 compatible = "snps,dw-apb-gpio";
148 reg = <0x70 0x3000b000 0x0 0x400>;
149 #address-cells = <1>;
150 #size-cells = <0>;
153 clock-names = "bus", "db";
155 port2a: gpio-controller@0 {
156 compatible = "snps,dw-apb-gpio-port";
157 gpio-controller;
158 #gpio-cells = <2>;
160 reg = <0>;
161 interrupt-controller;
162 #interrupt-cells = <2>;
163 interrupt-parent = <&intc>;
168 pllclk: clock-controller@70300100c0 {
169 compatible = "sophgo,sg2042-pll";
170 reg = <0x70 0x300100c0 0x0 0x40>;
172 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
173 #clock-cells = <1>;
176 rpgate: clock-controller@7030010368 {
177 compatible = "sophgo,sg2042-rpgate";
178 reg = <0x70 0x30010368 0x0 0x98>;
180 clock-names = "rpgate";
181 #clock-cells = <1>;
184 clkgen: clock-controller@7030012000 {
185 compatible = "sophgo,sg2042-clkgen";
186 reg = <0x70 0x30012000 0x0 0x1000>;
191 clock-names = "mpll",
195 #clock-cells = <1>;
198 clint_mswi: interrupt-controller@7094000000 {
199 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
200 reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
201 interrupts-extended = <&cpu0_intc 3>,
268 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
269 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
270 reg-names = "mtimecmp";
271 interrupts-extended = <&cpu0_intc 7>,
272 <&cpu1_intc 7>,
273 <&cpu2_intc 7>,
274 <&cpu3_intc 7>;
278 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
279 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
280 reg-names = "mtimecmp";
281 interrupts-extended = <&cpu4_intc 7>,
282 <&cpu5_intc 7>,
283 <&cpu6_intc 7>,
284 <&cpu7_intc 7>;
288 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
289 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
290 reg-names = "mtimecmp";
291 interrupts-extended = <&cpu8_intc 7>,
292 <&cpu9_intc 7>,
293 <&cpu10_intc 7>,
294 <&cpu11_intc 7>;
298 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
299 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
300 reg-names = "mtimecmp";
301 interrupts-extended = <&cpu12_intc 7>,
302 <&cpu13_intc 7>,
303 <&cpu14_intc 7>,
304 <&cpu15_intc 7>;
308 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
309 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
310 reg-names = "mtimecmp";
311 interrupts-extended = <&cpu16_intc 7>,
312 <&cpu17_intc 7>,
313 <&cpu18_intc 7>,
314 <&cpu19_intc 7>;
318 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
319 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
320 reg-names = "mtimecmp";
321 interrupts-extended = <&cpu20_intc 7>,
322 <&cpu21_intc 7>,
323 <&cpu22_intc 7>,
324 <&cpu23_intc 7>;
328 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
329 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
330 reg-names = "mtimecmp";
331 interrupts-extended = <&cpu24_intc 7>,
332 <&cpu25_intc 7>,
333 <&cpu26_intc 7>,
334 <&cpu27_intc 7>;
338 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
339 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
340 reg-names = "mtimecmp";
341 interrupts-extended = <&cpu28_intc 7>,
342 <&cpu29_intc 7>,
343 <&cpu30_intc 7>,
344 <&cpu31_intc 7>;
348 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
349 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
350 reg-names = "mtimecmp";
351 interrupts-extended = <&cpu32_intc 7>,
352 <&cpu33_intc 7>,
353 <&cpu34_intc 7>,
354 <&cpu35_intc 7>;
358 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
359 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
360 reg-names = "mtimecmp";
361 interrupts-extended = <&cpu36_intc 7>,
362 <&cpu37_intc 7>,
363 <&cpu38_intc 7>,
364 <&cpu39_intc 7>;
368 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
369 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
370 reg-names = "mtimecmp";
371 interrupts-extended = <&cpu40_intc 7>,
372 <&cpu41_intc 7>,
373 <&cpu42_intc 7>,
374 <&cpu43_intc 7>;
378 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
379 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
380 reg-names = "mtimecmp";
381 interrupts-extended = <&cpu44_intc 7>,
382 <&cpu45_intc 7>,
383 <&cpu46_intc 7>,
384 <&cpu47_intc 7>;
388 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
389 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
390 reg-names = "mtimecmp";
391 interrupts-extended = <&cpu48_intc 7>,
392 <&cpu49_intc 7>,
393 <&cpu50_intc 7>,
394 <&cpu51_intc 7>;
398 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
399 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
400 reg-names = "mtimecmp";
401 interrupts-extended = <&cpu52_intc 7>,
402 <&cpu53_intc 7>,
403 <&cpu54_intc 7>,
404 <&cpu55_intc 7>;
408 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
409 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
410 reg-names = "mtimecmp";
411 interrupts-extended = <&cpu56_intc 7>,
412 <&cpu57_intc 7>,
413 <&cpu58_intc 7>,
414 <&cpu59_intc 7>;
418 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
419 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
420 reg-names = "mtimecmp";
421 interrupts-extended = <&cpu60_intc 7>,
422 <&cpu61_intc 7>,
423 <&cpu62_intc 7>,
424 <&cpu63_intc 7>;
427 intc: interrupt-controller@7090000000 {
428 compatible = "sophgo,sg2042-plic", "thead,c900-plic";
429 #address-cells = <0>;
430 #interrupt-cells = <2>;
431 reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
432 interrupt-controller;
433 interrupts-extended =
501 rstgen: reset-controller@7030013000 {
502 compatible = "sophgo,sg2042-reset";
503 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
504 #reset-cells = <1>;
508 compatible = "snps,dw-apb-uart";
509 reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
511 clock-frequency = <500000000>;
514 clock-names = "baudclk", "apb_pclk";
515 reg-shift = <2>;
516 reg-io-width = <4>;
522 compatible = "sophgo,sg2042-dwcmshc";
523 reg = <0x70 0x4002a000 0x0 0x1000>;
524 interrupt-parent = <&intc>;
529 clock-names = "core",
536 compatible = "sophgo,sg2042-dwcmshc";
537 reg = <0x70 0x4002b000 0x0 0x1000>;
538 interrupt-parent = <&intc>;
543 clock-names = "core",