Lines Matching +full:event +full:- +full:to +full:- +full:mhpmcounters
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <[email protected]>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
23 i-cache-sets = <128>;
24 i-cache-size = <32768>;
25 mmu-type = "riscv,sv39";
26 operating-points-v2 = <&opp_table_cpu>;
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
32 #cooling-cells = <2>;
34 cpu0_intc: interrupt-controller {
35 compatible = "riscv,cpu-intc";
36 interrupt-controller;
37 #interrupt-cells = <1>;
42 opp_table_cpu: opp-table-cpu {
43 compatible = "operating-points-v2";
45 opp-408000000 {
46 opp-hz = /bits/ 64 <408000000>;
47 opp-microvolt = <900000 900000 1100000>;
50 opp-1080000000 {
51 opp-hz = /bits/ 64 <1008000000>;
52 opp-microvolt = <900000 900000 1100000>;
57 interrupt-parent = <&plic>;
60 compatible = "allwinner,sun20i-d1-wdt";
64 clock-names = "hosc", "losc";
67 plic: interrupt-controller@10000000 {
68 compatible = "allwinner,sun20i-d1-plic",
69 "thead,c900-plic";
71 interrupts-extended = <&cpu0_intc 11>,
73 interrupt-controller;
75 #address-cells = <0>;
76 #interrupt-cells = <2>;
82 riscv,event-to-mhpmcounters =
93 riscv,event-to-mhpmevent =
104 riscv,raw-event-to-mhpmcounters =