Lines Matching +full:ax45mp +full:- +full:cache
4 bool "Andes AX45MP errata"
14 bool "Apply Andes cache management errata"
19 This will apply the cache management errata to handle the
20 non-standard handling on non-coherent operations on Andes cores.
35 bool "Apply SiFive errata CIP-453"
39 This will apply the SiFive CIP-453 errata to add sign extension
46 bool "Apply SiFive errata CIP-1200"
50 This will apply the SiFive CIP-1200 errata to repalce all
68 caches that are non-coherent with respect to peripheral DMAs.
69 It was designed before the Zicbom extension so needs non-standard
70 cache operations through the SiFive cache controller.
76 bool "T-HEAD errata"
79 All T-HEAD errata Kconfig depend on this Kconfig. Disabling
80 this Kconfig will disable all T-HEAD errata. Please say "Y"
81 here if your platform uses T-HEAD CPU cores.
86 bool "Apply T-Head's memory attribute extension (XTheadMae) errata"
92 non-standard PTE utilization on T-Head SoCs (XTheadMae).
97 bool "Apply T-Head cache management errata"
104 This will apply the cache management errata to handle the
105 non-standard handling on non-coherent operations on T-Head SoCs.
110 bool "Apply T-Head PMU errata"
114 The T-Head C9xx cores implement a PMU overflow extension very
117 This will apply the overflow errata to handle the non-standard
123 bool "Apply T-Head Ghostwrite errata"
127 The T-Head C9xx cores have a vulnerability in the xtheadvector