Lines Matching full:opcode

1 /* ppc.h -- Header file for PowerPC opcode table
30 /* The opcode table is an array of struct powerpc_opcode.  */
34   /* The opcode name.  */
37   /* The opcode itself.  Those bits which will be filled in with
39   unsigned long opcode;  member
41   /* The opcode mask.  This is used by the disassembler.  This is a
43      opcode field, and zeroes indicating those bits which need not
47   /* One bit flags for the opcode.  These are used to indicate which
52   /* One bit flags for the opcode.  These are used to indicate which
63 /* The table itself is sorted by major opcode number, and is otherwise
73 /* Opcode is defined for the PowerPC architecture.  */
76 /* Opcode is defined for the POWER (RS/6000) architecture.  */
79 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
82 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
87 /* Opcode is supported in both the Power and PowerPC architectures
94 /* Opcode is supported for any Power or PowerPC platform (this is
98 /* Opcode is only defined on 64 bit architectures.  */
101 /* Opcode is supported as part of the 64-bit bridge.  */
104 /* Opcode is supported by Altivec Vector Unit */
107 /* Opcode is supported by PowerPC 403 processor.  */
110 /* Opcode is supported by PowerPC BookE processor.  */
113 /* Opcode is supported by PowerPC 440 processor.  */
116 /* Opcode is only supported by Power4 architecture.  */
119 /* Opcode is only supported by Power7 architecture.  */
122 /* Opcode is only supported by e500x2 Core.  */
125 /* Opcode is supported by e500x2 Integer select APU.  */
128 /* Opcode is an e500 SPE floating point instruction.  */
131 /* Opcode is supported by branch locking APU.  */
134 /* Opcode is supported by performance monitor APU.  */
137 /* Opcode is supported by cache locking APU.  */
140 /* Opcode is supported by machine check APU.  */
143 /* Opcode is only supported by Power5 architecture.  */
146 /* Opcode is supported by PowerPC e300 family.  */
149 /* Opcode is only supported by Power6 architecture.  */
152 /* Opcode is only supported by PowerPC Cell family.  */
155 /* Opcode is supported by CPUs with paired singles support.  */
158 /* Opcode is supported by Power E500MC */
161 /* Opcode is supported by PowerPC 405 processor.  */
164 /* Opcode is supported by Vector-Scalar (VSX) Unit */
167 /* Opcode is supported by A2.  */
170 /* Opcode is supported by PowerPC 476 processor.  */
173 /* Opcode is supported by AppliedMicro Titan core */
176 /* Opcode which is supported by the e500 family */
179 /* Opcode is supported by Extended Altivec Vector Unit */
182 /* Opcode is supported by Power E6500 */
185 /* Opcode is supported by Thread management APU */
188 /* Opcode which is supported by the VLE extension.  */
191 /* Opcode is only supported by Power8 architecture.  */
194 /* Opcode which is supported by the Hardware Transactional Memory extension.  */
199 /* Opcode is supported by ppc750cl.  */
202 /* Opcode is supported by ppc7450.  */
205 /* Opcode is supported by ppc821/850/860.  */
208 /* Opcode is only supported by Power9 architecture.  */
211 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
214   /* Opcode is supported by e200z4.  */
217 /* A macro to extract the major opcode from an instruction.  */
223 /* A macro to extract the major opcode from a VLE instruction.  */
226 /* A macro to convert a VLE opcode to a VLE opcode segment.  */
358    and the number of operands remaining for the opcode, and decide
365    1, ignoring the next operand field for the opcode.  This wretched
424   /* One bit flags for the opcode.  These are used to indicate which