1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * RCPM(Run Control/Power Management) support
5  * Copyright 2012-2015 Freescale Semiconductor Inc.
32 	setbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_mask()
33 	setbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_mask()
34 	setbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_mask()
35 	setbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_mask()
43 	setbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_mask()
44 	setbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_mask()
45 	setbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_mask()
46 	setbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_mask()
54 	clrbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_unmask()
55 	clrbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_unmask()
56 	clrbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_unmask()
57 	clrbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_unmask()
65 	clrbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_unmask()
66 	clrbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_unmask()
67 	clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_unmask()
68 	clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_unmask()
74 		setbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
76 		clrbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
82 		setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
84 		clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
94 		setbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_enter_state()
97 		setbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_enter_state()
113 		setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);  in rcpm_v2_cpu_enter_state()
116 		setbits32(&rcpm_v2_regs->pcph15setr, mask);  in rcpm_v2_cpu_enter_state()
119 		setbits32(&rcpm_v2_regs->pcph20setr, mask);  in rcpm_v2_cpu_enter_state()
122 		setbits32(&rcpm_v2_regs->pcph30setr, mask);  in rcpm_v2_cpu_enter_state()
148 	if (threads_per_core == 2) {  in rcpm_v2_cpu_die()
171 		clrbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_exit_state()
174 		clrbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_exit_state()
195 		setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);  in rcpm_v2_cpu_exit_state()
198 		setbits32(&rcpm_v2_regs->pcph15clrr, mask);  in rcpm_v2_cpu_exit_state()
201 		setbits32(&rcpm_v2_regs->pcph20clrr, mask);  in rcpm_v2_cpu_exit_state()
204 		setbits32(&rcpm_v2_regs->pcph30clrr, mask);  in rcpm_v2_cpu_exit_state()
219 	u32 *pmcsr_reg = &rcpm_v1_regs->powmgtcsr;  in rcpm_v1_plat_enter_state()
232 			ret = -ETIMEDOUT;  in rcpm_v1_plat_enter_state()
237 		ret = -EINVAL;  in rcpm_v1_plat_enter_state()
245 	u32 *pmcsr_reg = &rcpm_v2_regs->powmgtcsr;  in rcpm_v2_plat_enter_state()
263 			ret = -ETIMEDOUT;  in rcpm_v2_plat_enter_state()
268 		ret = -EINVAL;  in rcpm_v2_plat_enter_state()
301 	rcpm_common_freeze_time_base(&rcpm_v1_regs->ctbenr, freeze);  in rcpm_v1_freeze_time_base()
306 	rcpm_common_freeze_time_base(&rcpm_v2_regs->pctbenr, freeze);  in rcpm_v2_freeze_time_base()
342 		.compatible = "fsl,qoriq-rcpm-1.0",
346 		.compatible = "fsl,qoriq-rcpm-2.0",
350 		.compatible = "fsl,qoriq-rcpm-2.1",
370 		return -ENOMEM;  in fsl_rcpm_init()
379 	qoriq_pm_ops = match->data;  in fsl_rcpm_init()