Lines Matching full:pe
51 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
54 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, in pe_level_printk() argument
66 if (pe->flags & PNV_IODA_PE_DEV) in pe_level_printk()
67 strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); in pe_level_printk()
68 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) in pe_level_printk()
70 pci_domain_nr(pe->pbus), pe->pbus->number); in pe_level_printk()
72 else if (pe->flags & PNV_IODA_PE_VF) in pe_level_printk()
74 pci_domain_nr(pe->parent_dev->bus), in pe_level_printk()
75 (pe->rid & 0xff00) >> 8, in pe_level_printk()
76 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); in pe_level_printk()
79 printk("%spci %s: [PE# %.2x] %pV", in pe_level_printk()
80 level, pfix, pe->pe_number, &vaf); in pe_level_printk()
125 * Clear the PE frozen state as it might be put into frozen state in pnv_ioda_init_pe()
127 * PE is already in unfrozen state. in pnv_ioda_init_pe()
132 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", in pnv_ioda_init_pe()
141 pr_warn("%s: Invalid PE %x on PHB#%x\n", in pnv_ioda_reserve_pe()
148 pr_debug("%s: PE %x was reserved on PHB#%x\n", in pnv_ioda_reserve_pe()
158 int run = 0, pe, i; in pnv_ioda_alloc_pe() local
163 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { in pnv_ioda_alloc_pe()
164 if (test_bit(pe, phb->ioda.pe_alloc)) { in pnv_ioda_alloc_pe()
176 for (i = pe; i < pe + count; i++) { in pnv_ioda_alloc_pe()
180 ret = &phb->ioda.pe_array[pe]; in pnv_ioda_alloc_pe()
187 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) in pnv_ioda_free_pe() argument
189 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe()
190 unsigned int pe_num = pe->pe_number; in pnv_ioda_free_pe()
192 WARN_ON(pe->pdev); in pnv_ioda_free_pe()
193 memset(pe, 0, sizeof(struct pnv_ioda_pe)); in pnv_ioda_free_pe()
230 * Exclude the segments for reserved and root bus PE, which in pnv_ioda2_init_m64()
239 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", in pnv_ioda2_init_m64()
298 struct pnv_ioda_pe *master_pe, *pe; in pnv_ioda_pick_m64_pe() local
315 /* Figure out reserved PE numbers by the PE */ in pnv_ioda_pick_m64_pe()
321 * pick M64 dependent PE#. in pnv_ioda_pick_m64_pe()
329 * Figure out the master PE and put all slave PEs to master in pnv_ioda_pick_m64_pe()
330 * PE's list to form compound PE. in pnv_ioda_pick_m64_pe()
336 pe = &phb->ioda.pe_array[i]; in pnv_ioda_pick_m64_pe()
338 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; in pnv_ioda_pick_m64_pe()
340 pe->flags |= PNV_IODA_PE_MASTER; in pnv_ioda_pick_m64_pe()
341 INIT_LIST_HEAD(&pe->slaves); in pnv_ioda_pick_m64_pe()
342 master_pe = pe; in pnv_ioda_pick_m64_pe()
344 pe->flags |= PNV_IODA_PE_SLAVE; in pnv_ioda_pick_m64_pe()
345 pe->master = master_pe; in pnv_ioda_pick_m64_pe()
346 list_add_tail(&pe->list, &master_pe->slaves); in pnv_ioda_pick_m64_pe()
443 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_freeze_pe() local
447 /* Fetch master PE */ in pnv_ioda_freeze_pe()
448 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_freeze_pe()
449 pe = pe->master; in pnv_ioda_freeze_pe()
450 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) in pnv_ioda_freeze_pe()
453 pe_no = pe->pe_number; in pnv_ioda_freeze_pe()
456 /* Freeze master PE */ in pnv_ioda_freeze_pe()
461 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
467 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_freeze_pe()
470 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_freeze_pe()
475 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
483 struct pnv_ioda_pe *pe, *slave; in pnv_ioda_unfreeze_pe() local
486 /* Find master PE */ in pnv_ioda_unfreeze_pe()
487 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_unfreeze_pe()
488 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_unfreeze_pe()
489 pe = pe->master; in pnv_ioda_unfreeze_pe()
490 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_unfreeze_pe()
491 pe_no = pe->pe_number; in pnv_ioda_unfreeze_pe()
494 /* Clear frozen state for master PE */ in pnv_ioda_unfreeze_pe()
497 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
502 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_unfreeze_pe()
506 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_unfreeze_pe()
511 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
523 struct pnv_ioda_pe *slave, *pe; in pnv_ioda_get_pe_state() local
528 /* Sanity check on PE number */ in pnv_ioda_get_pe_state()
533 * Fetch the master PE and the PE instance might be in pnv_ioda_get_pe_state()
536 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_get_pe_state()
537 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_get_pe_state()
538 pe = pe->master; in pnv_ioda_get_pe_state()
539 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_get_pe_state()
540 pe_no = pe->pe_number; in pnv_ioda_get_pe_state()
543 /* Check the master PE */ in pnv_ioda_get_pe_state()
548 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
554 /* Check the slave PE */ in pnv_ioda_get_pe_state()
555 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_get_pe_state()
558 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_get_pe_state()
566 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
616 /* Parent PE affects child PE */ in pnv_ioda_set_one_peltv()
628 /* Compound case: parent PE affects slave PEs */ in pnv_ioda_set_one_peltv()
643 struct pnv_ioda_pe *pe, in pnv_ioda_set_peltv() argument
651 * Clear PE frozen state. If it's master PE, we need in pnv_ioda_set_peltv()
652 * clear slave PE frozen state as well. in pnv_ioda_set_peltv()
655 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_set_peltv()
657 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
658 list_for_each_entry(slave, &pe->slaves, list) in pnv_ioda_set_peltv()
666 * Associate PE in PELT. We need add the PE into the in pnv_ioda_set_peltv()
668 * originated from the PE might contribute to other in pnv_ioda_set_peltv()
671 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); in pnv_ioda_set_peltv()
676 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
677 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_set_peltv()
678 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); in pnv_ioda_set_peltv()
684 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) in pnv_ioda_set_peltv()
685 pdev = pe->pbus->self; in pnv_ioda_set_peltv()
686 else if (pe->flags & PNV_IODA_PE_DEV) in pnv_ioda_set_peltv()
687 pdev = pe->pdev->bus->self; in pnv_ioda_set_peltv()
689 else if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_set_peltv()
690 pdev = pe->parent_dev; in pnv_ioda_set_peltv()
698 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); in pnv_ioda_set_peltv()
710 struct pnv_ioda_pe *pe, in pnv_ioda_unset_peltv() argument
720 pe->pe_number, in pnv_ioda_unset_peltv()
727 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
730 /* Disassociate PE in PELT */ in pnv_ioda_unset_peltv()
731 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
732 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); in pnv_ioda_unset_peltv()
734 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); in pnv_ioda_unset_peltv()
737 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_deconfigure_pe() argument
744 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ in pnv_ioda_deconfigure_pe()
745 if (pe->pbus) { in pnv_ioda_deconfigure_pe()
750 parent = pe->pbus->self; in pnv_ioda_deconfigure_pe()
751 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_deconfigure_pe()
752 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_deconfigure_pe()
764 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_deconfigure_pe()
769 rid_end = pe->rid + (count << 8); in pnv_ioda_deconfigure_pe()
772 if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_deconfigure_pe()
773 parent = pe->parent_dev; in pnv_ioda_deconfigure_pe()
776 parent = pe->pdev->bus->self; in pnv_ioda_deconfigure_pe()
780 rid_end = pe->rid + 1; in pnv_ioda_deconfigure_pe()
784 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_deconfigure_pe()
792 pnv_ioda_unset_peltv(phb, pe, parent); in pnv_ioda_deconfigure_pe()
794 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_deconfigure_pe()
797 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); in pnv_ioda_deconfigure_pe()
799 pe->pbus = NULL; in pnv_ioda_deconfigure_pe()
800 pe->pdev = NULL; in pnv_ioda_deconfigure_pe()
802 pe->parent_dev = NULL; in pnv_ioda_deconfigure_pe()
808 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_configure_pe() argument
814 if (pe->pbus) { in pnv_ioda_configure_pe()
819 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_configure_pe()
820 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_configure_pe()
832 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_configure_pe()
837 rid_end = pe->rid + (count << 8); in pnv_ioda_configure_pe()
842 rid_end = pe->rid + 1; in pnv_ioda_configure_pe()
846 * Associate PE in PELT. We need add the PE into the in pnv_ioda_configure_pe()
848 * originated from the PE might contribute to other in pnv_ioda_configure_pe()
851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_configure_pe()
854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); in pnv_ioda_configure_pe()
863 pnv_ioda_set_peltv(phb, pe, true); in pnv_ioda_configure_pe()
866 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_configure_pe()
867 phb->ioda.pe_rmap[rid] = pe->pe_number; in pnv_ioda_configure_pe()
869 pe->mve_number = 0; in pnv_ioda_configure_pe()
878 struct pnv_ioda_pe *pe; in pnv_ioda_setup_dev_PE() local
888 pe = pnv_ioda_alloc_pe(phb, 1); in pnv_ioda_setup_dev_PE()
889 if (!pe) { in pnv_ioda_setup_dev_PE()
890 pr_warn("%s: Not enough PE# available, disabling device\n", in pnv_ioda_setup_dev_PE()
895 /* NOTE: We don't get a reference for the pointer in the PE in pnv_ioda_setup_dev_PE()
896 * data structure, both the device and PE structures should be in pnv_ioda_setup_dev_PE()
901 pdn->pe_number = pe->pe_number; in pnv_ioda_setup_dev_PE()
902 pe->flags = PNV_IODA_PE_DEV; in pnv_ioda_setup_dev_PE()
903 pe->pdev = dev; in pnv_ioda_setup_dev_PE()
904 pe->pbus = NULL; in pnv_ioda_setup_dev_PE()
905 pe->mve_number = -1; in pnv_ioda_setup_dev_PE()
906 pe->rid = dev->bus->number << 8 | pdn->devfn; in pnv_ioda_setup_dev_PE()
907 pe->device_count++; in pnv_ioda_setup_dev_PE()
909 pe_info(pe, "Associated device to PE\n"); in pnv_ioda_setup_dev_PE()
911 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_dev_PE()
913 pnv_ioda_free_pe(pe); in pnv_ioda_setup_dev_PE()
915 pe->pdev = NULL; in pnv_ioda_setup_dev_PE()
919 /* Put PE to the list */ in pnv_ioda_setup_dev_PE()
921 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_dev_PE()
923 return pe; in pnv_ioda_setup_dev_PE()
929 * subordinate PCI devices and buses. The second type of PE is normally
935 struct pnv_ioda_pe *pe = NULL; in pnv_ioda_setup_bus_PE() local
939 * In partial hotplug case, the PE instance might be still alive. in pnv_ioda_setup_bus_PE()
944 pe = &phb->ioda.pe_array[pe_num]; in pnv_ioda_setup_bus_PE()
948 /* PE number for root bus should have been reserved */ in pnv_ioda_setup_bus_PE()
950 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; in pnv_ioda_setup_bus_PE()
952 /* Check if PE is determined by M64 */ in pnv_ioda_setup_bus_PE()
953 if (!pe) in pnv_ioda_setup_bus_PE()
954 pe = pnv_ioda_pick_m64_pe(bus, all); in pnv_ioda_setup_bus_PE()
956 /* The PE number isn't pinned by M64 */ in pnv_ioda_setup_bus_PE()
957 if (!pe) in pnv_ioda_setup_bus_PE()
958 pe = pnv_ioda_alloc_pe(phb, 1); in pnv_ioda_setup_bus_PE()
960 if (!pe) { in pnv_ioda_setup_bus_PE()
961 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", in pnv_ioda_setup_bus_PE()
966 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); in pnv_ioda_setup_bus_PE()
967 pe->pbus = bus; in pnv_ioda_setup_bus_PE()
968 pe->pdev = NULL; in pnv_ioda_setup_bus_PE()
969 pe->mve_number = -1; in pnv_ioda_setup_bus_PE()
970 pe->rid = bus->busn_res.start << 8; in pnv_ioda_setup_bus_PE()
973 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", in pnv_ioda_setup_bus_PE()
975 pe->pe_number); in pnv_ioda_setup_bus_PE()
977 pe_info(pe, "Secondary bus %pad associated with PE#%x\n", in pnv_ioda_setup_bus_PE()
978 &bus->busn_res.start, pe->pe_number); in pnv_ioda_setup_bus_PE()
980 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_bus_PE()
982 pnv_ioda_free_pe(pe); in pnv_ioda_setup_bus_PE()
983 pe->pbus = NULL; in pnv_ioda_setup_bus_PE()
987 /* Put PE to the list */ in pnv_ioda_setup_bus_PE()
988 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_bus_PE()
990 return pe; in pnv_ioda_setup_bus_PE()
997 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_dev_setup() local
999 /* Check if the BDFN for this device is associated with a PE yet */ in pnv_pci_ioda_dma_dev_setup()
1000 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev)); in pnv_pci_ioda_dma_dev_setup()
1001 if (!pe) { in pnv_pci_ioda_dma_dev_setup()
1007 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev)); in pnv_pci_ioda_dma_dev_setup()
1008 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); in pnv_pci_ioda_dma_dev_setup()
1012 * If we can't setup the IODA PE something has gone horribly in pnv_pci_ioda_dma_dev_setup()
1015 if (WARN_ON(!pe)) in pnv_pci_ioda_dma_dev_setup()
1018 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); in pnv_pci_ioda_dma_dev_setup()
1025 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { in pnv_pci_ioda_dma_dev_setup()
1028 pnv_pci_ioda2_setup_dma_pe(phb, pe); in pnv_pci_ioda_dma_dev_setup()
1037 pdn->pe_number = pe->pe_number; in pnv_pci_ioda_dma_dev_setup()
1038 pe->device_count++; in pnv_pci_ioda_dma_dev_setup()
1041 pdev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_pci_ioda_dma_dev_setup()
1042 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); in pnv_pci_ioda_dma_dev_setup()
1045 if (pe->table_group.group) in pnv_pci_ioda_dma_dev_setup()
1046 iommu_add_device(&pe->table_group, &pdev->dev); in pnv_pci_ioda_dma_dev_setup()
1052 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1066 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) in pnv_pci_ioda_dma_64bit_bypass() argument
1085 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, in pnv_pci_ioda_dma_64bit_bypass()
1101 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, in pnv_pci_ioda_dma_64bit_bypass()
1102 pe->pe_number, in pnv_pci_ioda_dma_64bit_bypass()
1104 (pe->pe_number << 1) + 0, in pnv_pci_ioda_dma_64bit_bypass()
1110 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); in pnv_pci_ioda_dma_64bit_bypass()
1114 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); in pnv_pci_ioda_dma_64bit_bypass()
1123 struct pnv_ioda_pe *pe; in pnv_pci_ioda_iommu_bypass_supported() local
1128 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_ioda_iommu_bypass_supported()
1129 if (pe->tce_bypass_enabled) { in pnv_pci_ioda_iommu_bypass_supported()
1130 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; in pnv_pci_ioda_iommu_bypass_supported()
1143 /* pe->pdev should be set if it's a single device, pe->pbus if not */ in pnv_pci_ioda_iommu_bypass_supported()
1144 (pe->device_count == 1 || !pe->pbus) && in pnv_pci_ioda_iommu_bypass_supported()
1147 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); in pnv_pci_ioda_iommu_bypass_supported()
1176 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) in pnv_pci_phb3_tce_invalidate_pe() argument
1178 /* 01xb - invalidate TCEs that match the specified PE# */ in pnv_pci_phb3_tce_invalidate_pe()
1179 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); in pnv_pci_phb3_tce_invalidate_pe()
1180 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate_pe()
1186 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, in pnv_pci_phb3_tce_invalidate() argument
1190 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); in pnv_pci_phb3_tce_invalidate()
1193 /* We'll invalidate DMA address in PE scope */ in pnv_pci_phb3_tce_invalidate()
1195 start |= (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate()
1210 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_tce_invalidate_pe() argument
1212 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate_pe()
1215 pnv_pci_phb3_tce_invalidate_pe(pe); in pnv_pci_ioda2_tce_invalidate_pe()
1218 pe->pe_number, 0, 0, 0); in pnv_pci_ioda2_tce_invalidate_pe()
1227 struct pnv_ioda_pe *pe = container_of(tgl->table_group, in pnv_pci_ioda2_tce_invalidate() local
1229 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate()
1233 pnv_pci_phb3_tce_invalidate(pe, shift, in pnv_pci_ioda2_tce_invalidate()
1238 pe->pe_number, 1u << shift, in pnv_pci_ioda2_tce_invalidate()
1280 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_set_window() local
1282 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_set_window()
1289 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", in pnv_pci_ioda2_set_window()
1294 * Map TCE table through TVT. The TVE index is the PE number in pnv_pci_ioda2_set_window()
1298 pe->pe_number, in pnv_pci_ioda2_set_window()
1299 (pe->pe_number << 1) + num, in pnv_pci_ioda2_set_window()
1305 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); in pnv_pci_ioda2_set_window()
1310 tbl, &pe->table_group); in pnv_pci_ioda2_set_window()
1311 pnv_pci_ioda2_tce_invalidate_pe(pe); in pnv_pci_ioda2_set_window()
1316 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) in pnv_pci_ioda2_set_bypass() argument
1318 uint16_t window_id = (pe->pe_number << 1 ) + 1; in pnv_pci_ioda2_set_bypass()
1321 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); in pnv_pci_ioda2_set_bypass()
1326 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1327 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1329 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1332 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1333 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1335 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1339 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); in pnv_pci_ioda2_set_bypass()
1341 pe->tce_bypass_enabled = enable; in pnv_pci_ioda2_set_bypass()
1348 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_create_table() local
1350 int nid = pe->phb->hose->node; in pnv_pci_ioda2_create_table()
1351 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; in pnv_pci_ioda2_create_table()
1374 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_default_config() argument
1416 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, in pnv_pci_ioda2_setup_default_config()
1419 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", in pnv_pci_ioda2_setup_default_config()
1427 if (window_size > pe->phb->ioda.m32_pci_base) { in pnv_pci_ioda2_setup_default_config()
1428 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; in pnv_pci_ioda2_setup_default_config()
1432 tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number; in pnv_pci_ioda2_setup_default_config()
1433 if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) in pnv_pci_ioda2_setup_default_config()
1434 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); in pnv_pci_ioda2_setup_default_config()
1438 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); in pnv_pci_ioda2_setup_default_config()
1443 pnv_pci_ioda2_set_bypass(pe, true); in pnv_pci_ioda2_setup_default_config()
1450 if (pe->pdev) in pnv_pci_ioda2_setup_default_config()
1451 set_iommu_table_base(&pe->pdev->dev, tbl); in pnv_pci_ioda2_setup_default_config()
1459 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_unset_window() local
1461 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_unset_window()
1464 pe_info(pe, "Removing DMA window #%d\n", num); in pnv_pci_ioda2_unset_window()
1466 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, in pnv_pci_ioda2_unset_window()
1467 (pe->pe_number << 1) + num, in pnv_pci_ioda2_unset_window()
1471 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); in pnv_pci_ioda2_unset_window()
1473 pnv_pci_ioda2_tce_invalidate_pe(pe); in pnv_pci_ioda2_unset_window()
1527 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) in pnv_ioda_setup_bus_dma() argument
1532 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); in pnv_ioda_setup_bus_dma()
1533 dev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_ioda_setup_bus_dma()
1535 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) in pnv_ioda_setup_bus_dma()
1536 pnv_ioda_setup_bus_dma(pe, dev->subordinate); in pnv_ioda_setup_bus_dma()
1543 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_ioda2_take_ownership() local
1546 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_ioda2_take_ownership()
1555 pnv_pci_ioda2_set_bypass(pe, false); in pnv_ioda2_take_ownership()
1556 pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_ioda2_take_ownership()
1557 if (pe->pbus) in pnv_ioda2_take_ownership()
1558 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_take_ownership()
1559 else if (pe->pdev) in pnv_ioda2_take_ownership()
1560 set_iommu_table_base(&pe->pdev->dev, NULL); in pnv_ioda2_take_ownership()
1569 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_ioda2_release_ownership() local
1573 if (pe->table_group.tables[0]) in pnv_ioda2_release_ownership()
1575 pnv_pci_ioda2_setup_default_config(pe); in pnv_ioda2_release_ownership()
1576 if (pe->pbus) in pnv_ioda2_release_ownership()
1577 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_release_ownership()
1591 struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_dma_pe() argument
1596 pe->tce_bypass_base = 1ull << 59; in pnv_pci_ioda2_setup_dma_pe()
1598 /* The PE will reserve all possible 32-bits space */ in pnv_pci_ioda2_setup_dma_pe()
1599 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", in pnv_pci_ioda2_setup_dma_pe()
1603 pe->table_group.tce32_start = 0; in pnv_pci_ioda2_setup_dma_pe()
1604 pe->table_group.tce32_size = phb->ioda.m32_pci_base; in pnv_pci_ioda2_setup_dma_pe()
1605 pe->table_group.max_dynamic_windows_supported = in pnv_pci_ioda2_setup_dma_pe()
1607 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; in pnv_pci_ioda2_setup_dma_pe()
1608 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); in pnv_pci_ioda2_setup_dma_pe()
1610 rc = pnv_pci_ioda2_setup_default_config(pe); in pnv_pci_ioda2_setup_dma_pe()
1615 pe->table_group.ops = &pnv_pci_ioda2_ops; in pnv_pci_ioda2_setup_dma_pe()
1616 iommu_register_group(&pe->table_group, phb->hose->global_number, in pnv_pci_ioda2_setup_dma_pe()
1617 pe->pe_number); in pnv_pci_ioda2_setup_dma_pe()
1619 pe->dma_setup_done = true; in pnv_pci_ioda2_setup_dma_pe()
1696 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); in __pnv_pci_ioda_msi_setup() local
1703 /* No PE assigned ? bail out ... no MSI for you ! */ in __pnv_pci_ioda_msi_setup()
1704 if (pe == NULL) in __pnv_pci_ioda_msi_setup()
1708 if (pe->mve_number < 0) in __pnv_pci_ioda_msi_setup()
1715 /* Assign XIVE to PE */ in __pnv_pci_ioda_msi_setup()
1716 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); in __pnv_pci_ioda_msi_setup()
1718 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", in __pnv_pci_ioda_msi_setup()
1726 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, in __pnv_pci_ioda_msi_setup()
1738 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, in __pnv_pci_ioda_msi_setup()
1983 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, in pnv_ioda_setup_pe_res() argument
1986 struct pnv_phb *phb = pe->phb; in pnv_ioda_setup_pe_res()
2002 phb->ioda.io_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
2004 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
2006 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", in pnv_ioda_setup_pe_res()
2007 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
2026 phb->ioda.m32_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
2028 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
2030 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", in pnv_ioda_setup_pe_res()
2031 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
2042 * This function is supposed to be called on basis of PE from top
2044 * parent PE could be overridden by its child PEs if necessary.
2046 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) in pnv_ioda_setup_pe_seg() argument
2052 * NOTE: We only care PCI bus based PE for now. For PCI in pnv_ioda_setup_pe_seg()
2053 * device based PE, for example SRIOV sensitive VF should in pnv_ioda_setup_pe_seg()
2056 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); in pnv_ioda_setup_pe_seg()
2058 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { in pnv_ioda_setup_pe_seg()
2060 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); in pnv_ioda_setup_pe_seg()
2063 * If the PE contains all subordinate PCI buses, the in pnv_ioda_setup_pe_seg()
2065 * the PE as well. in pnv_ioda_setup_pe_seg()
2067 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) in pnv_ioda_setup_pe_seg()
2070 pnv_ioda_setup_pe_res(pe, in pnv_ioda_setup_pe_seg()
2101 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; in pnv_pci_ioda_pe_dump() local
2106 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", in pnv_pci_ioda_pe_dump()
2107 pe->rid, pe->device_count, in pnv_pci_ioda_pe_dump()
2108 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", in pnv_pci_ioda_pe_dump()
2109 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", in pnv_pci_ioda_pe_dump()
2110 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", in pnv_pci_ioda_pe_dump()
2111 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", in pnv_pci_ioda_pe_dump()
2112 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", in pnv_pci_ioda_pe_dump()
2113 (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); in pnv_pci_ioda_pe_dump()
2194 * For now, we return I/O or M32 segment size for PE sensitive
2198 * The current PCI bus might be put into one PE, which was
2295 struct pnv_ioda_pe *pe; in pnv_pci_configure_bus() local
2298 dev_info(&bus->dev, "Configuring PE for bus\n"); in pnv_pci_configure_bus()
2300 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ in pnv_pci_configure_bus()
2308 * Assign PE. We might run here because of partial hotplug. in pnv_pci_configure_bus()
2309 * For the case, we just pick up the existing PE and should in pnv_pci_configure_bus()
2312 pe = pnv_ioda_setup_bus_PE(bus, all); in pnv_pci_configure_bus()
2313 if (!pe) in pnv_pci_configure_bus()
2316 pnv_ioda_setup_pe_seg(pe); in pnv_pci_configure_bus()
2325 * assign a PE
2333 pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); in pnv_pci_enable_device_hook()
2343 struct pnv_ioda_pe *pe; in pnv_ocapi_enable_device_hook() local
2350 pe = pnv_ioda_setup_dev_PE(dev); in pnv_ocapi_enable_device_hook()
2351 if (!pe) in pnv_ocapi_enable_device_hook()
2357 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_release_pe_dma() argument
2359 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_pci_ioda2_release_pe_dma()
2362 if (!pe->dma_setup_done) in pnv_pci_ioda2_release_pe_dma()
2365 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_pci_ioda2_release_pe_dma()
2367 pe_warn(pe, "OPAL error %lld release DMA window\n", rc); in pnv_pci_ioda2_release_pe_dma()
2369 pnv_pci_ioda2_set_bypass(pe, false); in pnv_pci_ioda2_release_pe_dma()
2370 if (pe->table_group.group) { in pnv_pci_ioda2_release_pe_dma()
2371 iommu_group_put(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2372 WARN_ON(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2378 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, in pnv_ioda_free_pe_seg() argument
2382 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe_seg()
2387 if (map[idx] != pe->pe_number) in pnv_ioda_free_pe_seg()
2394 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", in pnv_ioda_free_pe_seg()
2401 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) in pnv_ioda_release_pe_seg() argument
2403 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe_seg()
2406 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, in pnv_ioda_release_pe_seg()
2411 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) in pnv_ioda_release_pe() argument
2413 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe()
2416 pe_info(pe, "Releasing PE\n"); in pnv_ioda_release_pe()
2419 list_del(&pe->list); in pnv_ioda_release_pe()
2424 pnv_pci_ioda2_release_pe_dma(pe); in pnv_ioda_release_pe()
2432 pnv_ioda_release_pe_seg(pe); in pnv_ioda_release_pe()
2433 pnv_ioda_deconfigure_pe(pe->phb, pe); in pnv_ioda_release_pe()
2435 /* Release slave PEs in the compound PE */ in pnv_ioda_release_pe()
2436 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_release_pe()
2437 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { in pnv_ioda_release_pe()
2444 * The PE for root bus can be removed because of hotplug in EEH in pnv_ioda_release_pe()
2445 * recovery for fenced PHB error. We need to mark the PE dead so in pnv_ioda_release_pe()
2446 * that it can be populated again in PCI hot add path. The PE in pnv_ioda_release_pe()
2449 if (phb->ioda.root_pe_idx == pe->pe_number) in pnv_ioda_release_pe()
2452 pnv_ioda_free_pe(pe); in pnv_ioda_release_pe()
2459 struct pnv_ioda_pe *pe; in pnv_pci_release_device() local
2461 /* The VF PE state is torn down when sriov_disable() is called */ in pnv_pci_release_device()
2481 * set the PE number in @pdn to an invalid one. Otherwise, the PE's in pnv_pci_release_device()
2483 * be increased on adding devices. It leads to unbalanced PE's device in pnv_pci_release_device()
2486 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_release_device()
2489 WARN_ON(--pe->device_count < 0); in pnv_pci_release_device()
2490 if (pe->device_count == 0) in pnv_pci_release_device()
2491 pnv_ioda_release_pe(pe); in pnv_pci_release_device()
2505 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_bus_setup() local
2507 list_for_each_entry(pe, &phb->ioda.pe_list, list) { in pnv_pci_ioda_dma_bus_setup()
2508 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) in pnv_pci_ioda_dma_bus_setup()
2511 if (!pe->pbus) in pnv_pci_ioda_dma_bus_setup()
2514 if (bus->number == ((pe->rid >> 8) & 0xFF)) { in pnv_pci_ioda_dma_bus_setup()
2515 pe->pbus = bus; in pnv_pci_ioda_dma_bus_setup()
2526 struct pnv_ioda_pe *pe; in pnv_pci_device_group() local
2531 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev)); in pnv_pci_device_group()
2532 if (!pe) in pnv_pci_device_group()
2535 if (!pe->table_group.group) in pnv_pci_device_group()
2538 return iommu_group_ref_get(pe->table_group.group); in pnv_pci_device_group()
2660 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); in pnv_pci_init_ioda_phb()
2664 /* Invalidate RID to PE# mapping */ in pnv_pci_init_ioda_phb()
2704 * Choose PE number for root bus, which shouldn't have in pnv_pci_init_ioda_phb()
2706 * the PE number adjacent to the reserved one if possible. in pnv_pci_init_ioda_phb()
2733 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", in pnv_pci_init_ioda_phb()
2757 * the child P2P bridges) can form individual PE. in pnv_pci_init_ioda_phb()