Lines Matching full:pe
70 struct eeh_pe *pe; in pnv_eeh_ei_write() local
90 /* Retrieve PE */ in pnv_eeh_ei_write()
91 pe = eeh_pe_get(hose, pe_no); in pnv_eeh_ei_write()
92 if (!pe) in pnv_eeh_ei_write()
96 ret = eeh_ops->err_inject(pe, type, func, addr, mask); in pnv_eeh_ei_write()
155 * to clear frozen PE during PCI config access. in pnv_eeh_enable_phbs()
300 /* for VFs we use the PF's PE as the upstream PE */ in pnv_eeh_get_upstream_pe()
305 /* otherwise use the PE of our parent bridge */ in pnv_eeh_get_upstream_pe()
338 if (!edev || edev->pe) in pnv_eeh_probe()
378 /* Create PE */ in pnv_eeh_probe()
381 eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); in pnv_eeh_probe()
386 * If the PE contains any one of following adapters, the in pnv_eeh_probe()
390 * should be blocked until PE reset. MMIO access is dropped in pnv_eeh_probe()
393 * will be checked in the backend for PE state retrieval. If in pnv_eeh_probe()
394 * the PE becomes frozen for the first time and the flag has in pnv_eeh_probe()
395 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for in pnv_eeh_probe()
396 * that PE to block its config space. in pnv_eeh_probe()
411 edev->pe->state |= EEH_PE_CFG_RESTRICTED; in pnv_eeh_probe()
414 * Cache the PE primary bus, which can't be fetched when in pnv_eeh_probe()
416 * PCI devices of the PE are expected to be removed prior in pnv_eeh_probe()
417 * to PE reset. in pnv_eeh_probe()
419 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { in pnv_eeh_probe()
420 edev->pe->bus = pci_find_bus(hose->global_number, in pnv_eeh_probe()
422 if (edev->pe->bus) in pnv_eeh_probe()
423 edev->pe->state |= EEH_PE_PRI_BUS; in pnv_eeh_probe()
446 * @pe: EEH PE
453 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) in pnv_eeh_set_option() argument
455 struct pci_controller *hose = pe->phb; in pnv_eeh_set_option()
484 phb->freeze_pe(phb, pe->addr); in pnv_eeh_set_option()
488 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); in pnv_eeh_set_option()
490 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_eeh_set_option()
492 pe->addr); in pnv_eeh_set_option()
501 return phb->unfreeze_pe(phb, pe->addr, opt); in pnv_eeh_set_option()
503 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); in pnv_eeh_set_option()
505 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", in pnv_eeh_set_option()
507 pe->addr); in pnv_eeh_set_option()
514 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) in pnv_eeh_get_phb_diag() argument
516 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_phb_diag()
519 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, in pnv_eeh_get_phb_diag()
523 __func__, rc, pe->phb->global_number); in pnv_eeh_get_phb_diag()
526 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) in pnv_eeh_get_phb_state() argument
528 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_phb_state()
535 pe->addr, in pnv_eeh_get_phb_state()
554 } else if (!(pe->state & EEH_PE_ISOLATED)) { in pnv_eeh_get_phb_state()
555 eeh_pe_mark_isolated(pe); in pnv_eeh_get_phb_state()
556 pnv_eeh_get_phb_diag(pe); in pnv_eeh_get_phb_state()
559 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_phb_state()
565 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) in pnv_eeh_get_pe_state() argument
567 struct pnv_phb *phb = pe->phb->private_data; in pnv_eeh_get_pe_state()
574 * We don't clobber hardware frozen state until PE in pnv_eeh_get_pe_state()
577 * state during PE reset. in pnv_eeh_get_pe_state()
579 if (pe->state & EEH_PE_RESET) { in pnv_eeh_get_pe_state()
588 * Fetch PE state from hardware. If the PHB in pnv_eeh_get_pe_state()
589 * supports compound PE, let it handle that. in pnv_eeh_get_pe_state()
592 fstate = phb->get_pe_state(phb, pe->addr); in pnv_eeh_get_pe_state()
595 pe->addr, in pnv_eeh_get_pe_state()
600 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", in pnv_eeh_get_pe_state()
602 pe->addr); in pnv_eeh_get_pe_state()
637 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", in pnv_eeh_get_pe_state()
639 pe->addr, fstate); in pnv_eeh_get_pe_state()
643 * If PHB supports compound PE, to freeze all in pnv_eeh_get_pe_state()
646 * If the PE is switching to frozen state for the in pnv_eeh_get_pe_state()
653 !(pe->state & EEH_PE_ISOLATED)) { in pnv_eeh_get_pe_state()
655 phb->freeze_pe(phb, pe->addr); in pnv_eeh_get_pe_state()
657 eeh_pe_mark_isolated(pe); in pnv_eeh_get_pe_state()
658 pnv_eeh_get_phb_diag(pe); in pnv_eeh_get_pe_state()
661 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_pe_state()
668 * pnv_eeh_get_state - Retrieve PE state
669 * @pe: EEH PE
670 * @delay: delay while PE state is temporarily unavailable
672 * Retrieve the state of the specified PE. For IODA-compitable
677 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) in pnv_eeh_get_state() argument
681 if (pe->type & EEH_PE_PHB) in pnv_eeh_get_state()
682 ret = pnv_eeh_get_phb_state(pe); in pnv_eeh_get_state()
684 ret = pnv_eeh_get_pe_state(pe); in pnv_eeh_get_state()
690 * If the PE state is temporarily unavailable, in pnv_eeh_get_state()
1002 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) in pnv_eeh_reset_vf_pe() argument
1008 /* The VF PE should have only one child device */ in pnv_eeh_reset_vf_pe()
1009 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); in pnv_eeh_reset_vf_pe()
1022 * pnv_eeh_reset - Reset the specified PE
1023 * @pe: EEH PE
1026 * Do reset on the indicated PE. For PCI bus sensitive PE,
1029 * PCI device sensitive PE, we will try to reset the device
1033 static int pnv_eeh_reset(struct eeh_pe *pe, int option) in pnv_eeh_reset() argument
1035 struct pci_controller *hose = pe->phb; in pnv_eeh_reset()
1044 * For other PEs, we always have hot reset on the PE primary bus. in pnv_eeh_reset()
1047 * frozen state during PE reset. However, the good idea here from in pnv_eeh_reset()
1048 * benh is to keep frozen state before we get PE reset done completely in pnv_eeh_reset()
1050 * or MMIO access, which can incur recursive frozen PE during PE in pnv_eeh_reset()
1054 if (pe->type & EEH_PE_PHB) in pnv_eeh_reset()
1058 * The frozen PE might be caused by PAPR error injection in pnv_eeh_reset()
1060 * frozen PE as stated in the hardware spec. Unfortunately, in pnv_eeh_reset()
1078 if (pe->type & EEH_PE_VF) in pnv_eeh_reset()
1079 return pnv_eeh_reset_vf_pe(pe, option); in pnv_eeh_reset()
1081 bus = eeh_pe_bus_get(pe); in pnv_eeh_reset()
1083 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", in pnv_eeh_reset()
1084 __func__, pe->phb->global_number, pe->addr); in pnv_eeh_reset()
1124 * @pe: EEH PE
1129 * Retrieve the temporary or permanent error from the PE.
1131 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, in pnv_eeh_get_log() argument
1135 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); in pnv_eeh_get_log()
1141 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1142 * @pe: EEH PE
1145 * in the specified PE so that the mulfunctional PE would be recovered
1148 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) in pnv_eeh_configure_bridge() argument
1154 * pnv_pe_err_inject - Inject specified error to the indicated PE
1155 * @pe: the indicated PE
1162 * determined by @type and @func, to the indicated PE for
1165 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, in pnv_eeh_err_inject() argument
1168 struct pci_controller *hose = pe->phb; in pnv_eeh_err_inject()
1194 rc = opal_pci_err_inject(phb->opal_id, pe->addr, in pnv_eeh_err_inject()
1198 "%d-%d to PHB#%x-PE#%x\n", in pnv_eeh_err_inject()
1200 hose->global_number, pe->addr); in pnv_eeh_err_inject()
1211 if (!edev || !edev->pe) in pnv_eeh_cfg_blocked()
1216 * in VF PE. It relies on the EEH PCI config accessors. So we in pnv_eeh_cfg_blocked()
1219 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) in pnv_eeh_cfg_blocked()
1222 if (edev->pe->state & EEH_PE_CFG_BLOCKED) in pnv_eeh_cfg_blocked()
1340 u16 pe_no, struct eeh_pe **pe) in pnv_eeh_get_pe() argument
1347 * If PHB supports compound PE, to fetch in pnv_eeh_get_pe()
1348 * the master PE because slave PE is invisible in pnv_eeh_get_pe()
1359 /* Find the PE according to PE# */ in pnv_eeh_get_pe()
1364 /* Freeze the (compound) PE */ in pnv_eeh_get_pe()
1365 *pe = dev_pe; in pnv_eeh_get_pe()
1370 * At this point, we're sure the (compound) PE should in pnv_eeh_get_pe()
1372 * hitting the frozen PE on top level. in pnv_eeh_get_pe()
1383 /* Frozen parent PE */ in pnv_eeh_get_pe()
1384 *pe = dev_pe; in pnv_eeh_get_pe()
1397 * @pe: Affected PE
1400 * special EEH event (without binding PE). The function calls to
1403 * fenced PHB and frozen PE should be handled by EEH core eventually.
1405 static int pnv_eeh_next_error(struct eeh_pe **pe) in pnv_eeh_next_error() argument
1473 *pe = phb_pe; in pnv_eeh_next_error()
1481 *pe = phb_pe; in pnv_eeh_next_error()
1500 * If we can't find the corresponding PE, we in pnv_eeh_next_error()
1504 be64_to_cpu(frozen_pe_no), pe)) { in pnv_eeh_next_error()
1505 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", in pnv_eeh_next_error()
1522 } else if ((*pe)->state & EEH_PE_ISOLATED || in pnv_eeh_next_error()
1523 eeh_pe_passed(*pe)) { in pnv_eeh_next_error()
1526 pr_err("EEH: Frozen PE#%x " in pnv_eeh_next_error()
1528 (*pe)->addr, in pnv_eeh_next_error()
1529 (*pe)->phb->global_number); in pnv_eeh_next_error()
1530 pr_err("EEH: PE location: %s, " in pnv_eeh_next_error()
1532 eeh_pe_loc_get(*pe), in pnv_eeh_next_error()
1545 * frozen PE. In the time for frozen PE, EEH core in pnv_eeh_next_error()
1552 !((*pe)->state & EEH_PE_ISOLATED)) { in pnv_eeh_next_error()
1553 eeh_pe_mark_isolated(*pe); in pnv_eeh_next_error()
1554 pnv_eeh_get_phb_diag(*pe); in pnv_eeh_next_error()
1557 pnv_pci_dump_phb_diag_data((*pe)->phb, in pnv_eeh_next_error()
1558 (*pe)->data); in pnv_eeh_next_error()
1562 * We probably have the frozen parent PE out there and in pnv_eeh_next_error()
1563 * we need have to handle frozen parent PE firstly. in pnv_eeh_next_error()
1566 parent_pe = (*pe)->parent; in pnv_eeh_next_error()
1572 /* Frozen parent PE ? */ in pnv_eeh_next_error()
1575 *pe = parent_pe; in pnv_eeh_next_error()
1581 /* We possibly migrate to another PE */ in pnv_eeh_next_error()
1582 eeh_pe_mark_isolated(*pe); in pnv_eeh_next_error()
1664 * P7IOC blocks PCI config access to frozen PE, but PHB3 in eeh_powernv_init()