39 #define SVR_REV(svr)    (((svr) >>  0) & 0xFFFF) /* Revision field */
59 	ret = of_address_to_resource(np_par, 0, &res);  in quirk_mpc8360e_qe_enet10()
73 	 * write 0b01 to UCC1 bits 18:19  in quirk_mpc8360e_qe_enet10()
74 	 * write 0b01 to UCC2 option 1 bits 4:5  in quirk_mpc8360e_qe_enet10()
75 	 * write 0b01 to UCC2 option 2 bits 16:17  in quirk_mpc8360e_qe_enet10()
77 	clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);  in quirk_mpc8360e_qe_enet10()
83 	 * write 0b01 to UCC2 option 2 bits 16:17  in quirk_mpc8360e_qe_enet10()
84 	 * write 0b0101 to UCC1 bits 20:23  in quirk_mpc8360e_qe_enet10()
85 	 * write 0b0101 to UCC2 option 1 bits 24:27  in quirk_mpc8360e_qe_enet10()
87 	clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);  in quirk_mpc8360e_qe_enet10()
89 	if (SVR_REV(svid) == 0x0021) {  in quirk_mpc8360e_qe_enet10()
91 		 * UCC2 option 1: write 0b1010 to bits 24:27  in quirk_mpc8360e_qe_enet10()
92 		 * at address IMMRBAR+0x14AC  in quirk_mpc8360e_qe_enet10()
94 		clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);  in quirk_mpc8360e_qe_enet10()
95 	} else if (SVR_REV(svid) == 0x0020) {  in quirk_mpc8360e_qe_enet10()
97 		 * UCC1: write 0b11 to bits 18:19  in quirk_mpc8360e_qe_enet10()
98 		 * at address IMMRBAR+0x14A8  in quirk_mpc8360e_qe_enet10()
100 		setbits32((base + 0xa8), 0x00003000);  in quirk_mpc8360e_qe_enet10()
103 		 * UCC2 option 1: write 0b11 to bits 4:5  in quirk_mpc8360e_qe_enet10()
104 		 * at address IMMRBAR+0x14A8  in quirk_mpc8360e_qe_enet10()
106 		setbits32((base + 0xa8), 0x0c000000);  in quirk_mpc8360e_qe_enet10()
109 		 * UCC2 option 2: write 0b11 to bits 16:17  in quirk_mpc8360e_qe_enet10()
110 		 * at address IMMRBAR+0x14AC  in quirk_mpc8360e_qe_enet10()
112 		setbits32((base + 0xac), 0x0000c000);  in quirk_mpc8360e_qe_enet10()
168 	int i = 0;  in mpc83xx_km_probe()